a

Author: ThanhDo288

RicsV_pipelined/ALU.v renamed to RicsV_Pipelined310524/ALU.v

@@ -0,0 +1,32 @@
+module EX_MEM (
+    input clk,
+    input reset,
+    input RegWrite_E, MemWrite_E,
+    input [1:0] ResultSrc_E,    
+    input [31:0] ALUResult_E, Mux_RD2E_out, PCPlus4_E,
+    input [31:0] Rd_E,
+    output reg RegWrite_M, MemWrite_M,
+    output reg [1:0] ResultSrc_M,
+    output reg [31:0] ALUResult_M, WriteData_M, PCPlus4_M,
+    output reg [31:0] Rd_M
+);
+    always @(posedge clk or negedge reset) begin
+        if (!reset) begin
+            RegWrite_M <= 1'b0;
+            MemWrite_M <= 1'b0;
+            ResultSrc_M <= 2'b00;
+            ALUResult_M <= 32'b0;
+            WriteData_M <= 32'b0;
+            Rd_M <= 32'b0;
+            PCPlus4_M <= 32'b0;
+        end else begin
+            RegWrite_M <= RegWrite_E;
+            MemWrite_M <= MemWrite_E;
+            ResultSrc_M <= ResultSrc_E;
+            ALUResult_M <= ALUResult_E;
+            WriteData_M <= Mux_RD2E_out;
+            Rd_M <= Rd_E;
+            PCPlus4_M <= PCPlus4_E;
+        end
+    end
+endmodule

RicsV_pipelined/ALU_Control.v renamed to RicsV_Pipelined310524/ALU_Control.v

@@ -0,0 +1,39 @@
+module Hazard_Unit(
+    input [4:0] Rs1_E, Rs2_E, Rs1_D, Rs2_D,
+    input [4:0] Rd_M, Rd_W, Rd_E,
+    input ResultSrc_E0,
+    input RegWrite_M, RegWrite_W,
+    output reg [1:0] ForwardA_E, ForwardB_E,
+    output reg Stall_F, Stall_D, Flush_E
+);
+
+    // load word stall signal
+    wire lwStall;
+    assign lwStall = ((Rs1_D == Rd_E) || (Rs2_D == Rd_E)) && ResultSrc_E0;
+
+    // Assign stall and flush signals
+    always @(*) begin
+        Stall_F = lwStall;
+        Stall_D = lwStall;
+        Flush_E = lwStall;
+    end
+
+    // Forwarding logic
+    always @(*) begin
+        // Initialize outputs
+        ForwardA_E = 2'b00;
+        ForwardB_E = 2'b00;
+
+        // Forwarding logic for A
+        if ((Rs1_E == Rd_M) && RegWrite_M)
+            ForwardA_E = 2'b10;
+        else if ((Rs1_E == Rd_W) && RegWrite_W)
+            ForwardA_E = 2'b01;
+
+        // Forwarding logic for B
+        if ((Rs2_E == Rd_M) && RegWrite_M)
+            ForwardB_E = 2'b10;
+        else if ((Rs2_E == Rd_W) && RegWrite_W)
+            ForwardB_E = 2'b01;
+    end
+endmodule

RicsV_pipelined/Add_PC.v renamed to RicsV_Pipelined310524/Add_PC.v

@@ -0,0 +1,67 @@
+module ID_EX (
+    input clk,
+    input reset,
+    input Flush_E,
+    input RegWrite_D, MemWrite_D, Jump_D, Branch_D, ALUSrc_D,
+    input [1:0] ResultSrc_D,
+    input [3:0] ALUControl_D,
+    input [31:0] RD1_D, RD2_D, Extimm_D, PCplus4_D, PC_D,
+    input [31:0] Rs1_D, Rs2_D, Rd_D,
+    output reg RegWrite_E, MemWrite_E, Jump_E, Branch_E, ALUSrc_E,
+    output reg [1:0] ResultSrc_E,
+    output reg [3:0] ALUControl_E,
+    output reg [31:0] RD1_E, RD2_E, Extimm_E, PCplus4_E, PC_E,
+    output reg [31:0] Rs1_E, Rs2_E, Rd_E
+);
+    always @(posedge clk or negedge reset) begin
+        if (!reset) begin
+            RegWrite_E <= 1'b0;
+            MemWrite_E <= 1'b0;
+            Jump_E <= 1'b0;
+            Branch_E <= 1'b0;
+            ALUSrc_E <= 1'b0;
+            ResultSrc_E <= 2'b00;
+            ALUControl_E <= 4'b0000;
+            RD1_E <= 32'b0;
+            RD2_E <= 32'b0;
+            PC_E <= 32'b0;
+            Rs1_E <= 32'b0;
+            Rs2_E <= 32'b0;
+            Rd_E <= 32'b0;
+            Extimm_E <= 32'b0;
+            PCplus4_E <= 32'b0;
+        end else if (!Flush_E) begin
+            RegWrite_E <= RegWrite_D;
+            MemWrite_E <= MemWrite_D;
+            Jump_E <= Jump_D;
+            Branch_E <= Branch_D;
+            ALUSrc_E <= ALUSrc_D;
+            ResultSrc_E <= ResultSrc_D;
+            ALUControl_E <= ALUControl_D;
+            RD1_E <= RD1_D;
+            RD2_E <= RD2_D;
+            PC_E <= PC_D;
+            Rs1_E <= Rs1_D;
+            Rs2_E <= Rs2_D;
+            Rd_E <= Rd_D;
+            Extimm_E <= Extimm_D;
+            PCplus4_E <= PCplus4_D;
+        end else begin
+            RegWrite_E <= 1'b0;
+            MemWrite_E <= 1'b0;
+            Jump_E <= 1'b0;
+            Branch_E <= 1'b0;
+            ALUSrc_E <= 1'b0;
+            ResultSrc_E <= 2'b00;
+            ALUControl_E <= 4'b0000;
+            RD1_E <= 32'b0;
+            RD2_E <= 32'b0;
+            PC_E <= 32'b0;
+            Rs1_E <= 32'b0;
+            Rs2_E <= 32'b0;
+            Rd_E <= 32'b0;
+            Extimm_E <= 32'b0;
+            PCplus4_E <= 32'b0;
+        end
+    end
+endmodule

RicsV_pipelined/Control_Unit.v renamed to RicsV_Pipelined310524/Control_Unit.v

@@ -0,0 +1,25 @@
+module IF_ID (
+    input clk,
+    input reset,
+    input Stall_D,
+    input [31:0] Instr,
+    input [31:0] PCplus4_out,
+    input [31:0] PC_out,
+    output reg [31:0] Instruction_D,
+    output reg [31:0] PCplus4_D,
+    output reg [31:0] PC_D
+);
+    always @(posedge clk or negedge reset) begin
+        if (!reset) begin
+            Instruction_D <= 32'b0;
+            PCplus4_D <= 32'b0;
+            PC_D <= 32'b0;
+        end else begin
+            if (!Stall_D) begin
+                Instruction_D <= Instr;
+                PCplus4_D <= PCplus4_out;
+                PC_D <= PC_out;
+            end
+        end
+    end
+endmodule