Re-enable xsim for testcases. Works better in Vivado 2024.2

amykyta3 · amykyta3 · commit 833c515cd296 · 2025-04-11T22:19:19.000-07:00
diff --git a/tests/lib/simulators/xilinx.py b/tests/lib/simulators/xilinx.py
@@ -6,15 +6,6 @@
 from .base import Simulator
 
 class XilinxXSIM(Simulator):
-    """
-    Avoid using the Xilinx simulator... Its buggy and extraordinarily slow.
-    As observed in v2023.2:
-        - Clocking block assignments to struct members do not simulate correctly.
-          assignment statements get lost.
-            https://support.xilinx.com/s/question/0D54U00007ZIGfXSAX/xsim-bug-xsim-does-not-simulate-struct-assignments-in-clocking-blocks-correctly?language=en_US
-        - Streaming bit-swap within a conditional returns a corrupted value
-            https://support.xilinx.com/s/question/0D54U00007ZIIBPSA5/xsim-bug-xsim-corrupts-value-of-signal-that-is-bitswapped-within-a-conditional-operator?language=en_US
-    """
     name = "xsim"
 
     @classmethod
diff --git a/tests/lib/synthesizers/vivado_scripts/run.tcl b/tests/lib/synthesizers/vivado_scripts/run.tcl
@@ -22,7 +22,7 @@ set_msg_config -id {[Synth 8-295]} -new_severity "ERROR"
 set_msg_config -severity {CRITICAL WARNING} -new_severity "ERROR"
 
 
-set_part xczu7eg-ffvf1517-2-i
+set_part [lindex [get_parts] 0]
 read_verilog -sv $files
 read_xdc $this_dir/constr.xdc
 synth_design -top regblock -mode out_of_context
diff --git a/tests/test_buffered_swacc_swmod/testcase.py b/tests/test_buffered_swacc_swmod/testcase.py
@@ -1,6 +1,5 @@
 from ..lib.sim_testcase import SimTestCase
 
 class Test(SimTestCase):
-    incompatible_sim_tools = {"xsim"} # due to cb struct assignment bug
     def test_dut(self):
         self.run_test()
diff --git a/tests/test_counter_basics/testcase.py b/tests/test_counter_basics/testcase.py
@@ -1,6 +1,5 @@
 from ..lib.sim_testcase import SimTestCase
 
 class Test(SimTestCase):
-    incompatible_sim_tools = {"xsim"} # due to cb struct assignment bug
     def test_dut(self):
         self.run_test()
diff --git a/tests/test_field_types/testcase.py b/tests/test_field_types/testcase.py
@@ -1,6 +1,5 @@
 from ..lib.sim_testcase import SimTestCase
 
 class Test(SimTestCase):
-    incompatible_sim_tools = {"xsim"} # due to cb struct assignment bug
     def test_dut(self):
         self.run_test()
diff --git a/tests/test_hw_access/testcase.py b/tests/test_hw_access/testcase.py
@@ -1,6 +1,5 @@
 from ..lib.sim_testcase import SimTestCase
 
 class Test(SimTestCase):
-    incompatible_sim_tools = {"xsim"} # due to cb struct assignment bug
     def test_dut(self):
         self.run_test()
diff --git a/tests/test_interrupts/tb_template.sv b/tests/test_interrupts/tb_template.sv
@@ -112,7 +112,6 @@
     cpuif.assert_read('h10, 'h000);
     assert(cb.hwif_out.level_irqs_we.intr == 1'b0);
     cb.hwif_in.level_irqs_we.irq0.next <= 'h0F;
-    assert(cb.hwif_in.level_irqs_we.irq0.next == 8'h00);
     @cb;
     cb.hwif_in.level_irqs_we.irq0.next <= 'h00;
     assert(cb.hwif_out.level_irqs_we.intr == 1'b0);
@@ -123,7 +122,6 @@
     assert(cb.hwif_out.level_irqs_we.intr == 1'b0);
     cb.hwif_in.level_irqs_we.irq0.next <= 'h0F;
     @cb;
-    assert(cb.hwif_in.level_irqs_we.irq0.next == 8'h0F);
     cpuif.assert_read('h10, 'h00F);
     assert(cb.hwif_out.level_irqs_we.intr == 1'b1);
     cpuif.write('h110, 'h0); // disable ctrl_we
@@ -138,20 +136,16 @@
     cpuif.assert_read('h14, 'h000);
     assert(cb.hwif_out.level_irqs_wel.intr == 1'b0);
     cb.hwif_in.level_irqs_wel.irq0.next <= 'h0F;
-    assert(cb.hwif_in.level_irqs_wel.irq0.next == 8'h00);
     @cb;
     cb.hwif_in.level_irqs_wel.irq0.next <= 'h00;
     cpuif.assert_read('h14, 'h000);
-    assert(cb.hwif_in.level_irqs_wel.irq0.next == 8'h00);
     assert(cb.hwif_out.level_irqs_wel.intr == 1'b0);
     cpuif.write('h114, 'h2); // enable ctrl_we
     @cb;
     cpuif.assert_read('h14, 'h000);
-    assert(cb.hwif_in.level_irqs_wel.irq0.next == 8'h00);
     assert(cb.hwif_out.level_irqs_wel.intr == 1'b0);
     cb.hwif_in.level_irqs_wel.irq0.next <= 'h0F;
     @cb;
-    assert(cb.hwif_in.level_irqs_wel.irq0.next == 8'h0F);
     cpuif.assert_read('h14, 'h00F);
     assert(cb.hwif_out.level_irqs_wel.intr == 1'b1);
     cpuif.write('h114, 'h3); // disable ctrl_we
diff --git a/tests/test_interrupts/testcase.py b/tests/test_interrupts/testcase.py
@@ -1,6 +1,5 @@
 from ..lib.sim_testcase import SimTestCase
 
 class Test(SimTestCase):
-    incompatible_sim_tools = {"xsim"} # due to cb struct assignment bug
     def test_dut(self):
         self.run_test()
diff --git a/tests/test_precedence/testcase.py b/tests/test_precedence/testcase.py
@@ -1,6 +1,5 @@
 from ..lib.sim_testcase import SimTestCase
 
 class Test(SimTestCase):
-    incompatible_sim_tools = {"xsim"} # due to cb struct assignment bug
     def test_dut(self):
         self.run_test()
diff --git a/tests/test_read_buffer/testcase.py b/tests/test_read_buffer/testcase.py
@@ -1,6 +1,5 @@
 from ..lib.sim_testcase import SimTestCase
 
 class Test(SimTestCase):
-    incompatible_sim_tools = {"xsim"} # due to cb struct assignment bug
     def test_dut(self):
         self.run_test()
diff --git a/tests/test_reset_signals/testcase.py b/tests/test_reset_signals/testcase.py
@@ -1,6 +1,5 @@
 from ..lib.sim_testcase import SimTestCase
 
 class Test(SimTestCase):
-    incompatible_sim_tools = {"xsim"} # due to cb struct assignment bug
     def test_dut(self):
         self.run_test()
diff --git a/tests/test_structural_sw_rw/tb_template.sv b/tests/test_structural_sw_rw/tb_template.sv
@@ -71,13 +71,10 @@
     cpuif.assert_read('h3000, 'h4DEAB000);
 
     // rw_reg_lsb0
-    `ifndef XILINX_XSIM
-        // Skip due to xsim bug simulating internal RTL - bitswap inside conditional corrupts data
-        cpuif.assert_read('h3004, 0);
-        cpuif.write('h3004, 'h4DEAB000);
-        @cb;
-        assert(`bitswap(cb.hwif_out.rw_reg_lsb0.f1.value) == 8'hAB);
-        assert(`bitswap(cb.hwif_out.rw_reg_lsb0.f2.value) == 11'h4DE);
-        cpuif.assert_read('h3004, 'h4DEAB000);
-    `endif
+    cpuif.assert_read('h3004, 0);
+    cpuif.write('h3004, 'h4DEAB000);
+    @cb;
+    assert(`bitswap(cb.hwif_out.rw_reg_lsb0.f1.value) == 8'hAB);
+    assert(`bitswap(cb.hwif_out.rw_reg_lsb0.f2.value) == 11'h4DE);
+    cpuif.assert_read('h3004, 'h4DEAB000);
 {% endblock %}
diff --git a/tests/test_swacc_swmod/testcase.py b/tests/test_swacc_swmod/testcase.py
@@ -1,6 +1,5 @@
 from ..lib.sim_testcase import SimTestCase
 
 class Test(SimTestCase):
-    incompatible_sim_tools = {"xsim"} # due to cb struct assignment bug
     def test_dut(self):
         self.run_test()
diff --git a/tests/test_swwe/testcase.py b/tests/test_swwe/testcase.py
@@ -1,6 +1,5 @@
 from ..lib.sim_testcase import SimTestCase
 
 class Test(SimTestCase):
-    incompatible_sim_tools = {"xsim"} # due to cb struct assignment bug
     def test_dut(self):
         self.run_test()
diff --git a/tests/test_wide_regs/testcase.py b/tests/test_wide_regs/testcase.py
@@ -1,6 +1,5 @@
 from ..lib.sim_testcase import SimTestCase
 
 class Test(SimTestCase):
-    incompatible_sim_tools = {"xsim"} # due to cb struct assignment bug
     def test_dut(self):
         self.run_test()
diff --git a/tests/test_write_buffer/testcase.py b/tests/test_write_buffer/testcase.py
@@ -2,8 +2,6 @@
 from ..lib.cpuifs.passthrough import Passthrough
 
 class Test(SimTestCase):
-    incompatible_sim_tools = {"xsim"} # due to cb struct assignment bug
-
     cpuif = Passthrough() # test with bit strobes
 
     def test_dut(self):
