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v1.0.0.3

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@darsor darsor released this 30 Apr 21:32
v1.0.0.3+vhdl
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darsor Dana Sorensen
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darsor Dana Sorensen
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Learn about vigilant mode.

New VHDL Port of PeakRDL-regblock

This is the initial release of the VHDL port of PeakRDL-regblock v1.0.0. All features of the SystemVerilog exporter are supported. See the discussion on its relationship to the SystemVerilog exporter in the README.

⚠️ Note: this VHDL exporter is not yet ready for production. The 1.0.0.2 version is derived from the upstream release and does not reflect this repository's stability. Code coverage is good and unit tests pass, and we're not aware of any bugs, but it has not yet been put through its paces on real-world projects. Please report any issues encountered.

Changed

  • Updated documentation
  • Ported synthesis tests to VHDL
  • avalon_mm_intf_pkg.vhd no longer needed for flat avalon interface

Full Changelog: v1.0.0...v1.0.0.3+vhdl

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