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Sum_rep_Cadence
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1564 lines (1554 loc) · 65.4 KB
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###############################################################
# Generated by: Cadence Encounter 14.28-s033_1
# OS: Linux x86_64(Host ID Cadence_SERVER)
# Generated on: Thu May 12 12:26:03 2022
# Design: PWM
# Command: summaryReport -noHtml -outfile Summary_report
###############################################################
==============================
General Design Information
==============================
Design Status: Routed
Design Name: PWM
# Instances: 153
# Hard Macros: 0
# Std Cells: 153
------------------------------
Standard Cells in Netlist
------------------------------
Cell Type Instance Count Area (um^2)
AND2_X1 26 27.6640
AOI211_X1 1 1.3300
AOI21_X1 1 1.0640
AOI221_X1 1 1.5960
DFF_X1 30 135.6600
INV_X1 26 13.8320
NAND2_X1 26 20.7480
NOR2_X1 8 6.3840
NOR3_X1 1 1.0640
OAI22_X1 1 1.3300
XNOR2_X1 29 46.2840
XOR2_X1 3 4.7880
# Pads: 0
# Net: 189
# Special Net: 2
# IO Pins:
------------------------------
Issued IO Information
------------------------------
# Unplaced IO Pin 0
# Floating IO 0
# IO Connected to Non-IO Inst
------------------------------
IO Connected to Non-IO Inst
------------------------------
IO Name Non-IO Inst Name
LED g248
reset g86
clk pwm_cnt_reg[3] 3 3
# Pins:
------------------------------
Correctness of Pin Connectivity for All Instances
------------------------------
# Floating Terms 0
# Output Term Marked Tie Hi/Lo 0
# Output Term Shorted to PG Net 0 472
# PG Pins:
------------------------------
Correctness of PG Pin Connectivity for All Instances
------------------------------
# Instances that No Net Defined for Any PG Pin 0
# Floating PG Terms
------------------------------
Floating PG Terms
------------------------------
PG Term Name Instance Name
VSS g152
VDD g152
VSS g149
VDD g149
VSS g148
VDD g148
VSS g147
VDD g147
VSS g146
VDD g146
VSS g145
VDD g145
VSS g144
VDD g144
VSS g143
VDD g143
VSS g142
VDD g142
VSS g141
VDD g141
VSS g140
VDD g140
VSS g139
VDD g139
VSS g138
VDD g138
VSS g137
VDD g137
VSS g136
VDD g136
VSS g135
VDD g135
VSS g134
VDD g134
VSS g133
VDD g133
VSS g132
VDD g132
VSS g131
VDD g131
VSS g130
VDD g130
VSS g129
VDD g129
VSS g128
VDD g128
VSS g127
VDD g127
VSS g126
VDD g126
VSS g125
VDD g125
VSS g124
VDD g124
VSS g123
VDD g123
VSS g122
VDD g122
VSS g121
VDD g121
VSS g120
VDD g120
VSS cnt_reg[0]
VDD cnt_reg[0]
VSS cnt_reg[10]
VDD cnt_reg[10]
VSS cnt_reg[8]
VDD cnt_reg[8]
VSS cnt_reg[9]
VDD cnt_reg[9]
VSS cnt_reg[25]
VDD cnt_reg[25]
VSS cnt_reg[7]
VDD cnt_reg[7]
VSS cnt_reg[6]
VDD cnt_reg[6]
VSS cnt_reg[5]
VDD cnt_reg[5]
VSS cnt_reg[4]
VDD cnt_reg[4]
VSS cnt_reg[3]
VDD cnt_reg[3]
VSS cnt_reg[2]
VDD cnt_reg[2]
VSS cnt_reg[26]
VDD cnt_reg[26]
VSS cnt_reg[24]
VDD cnt_reg[24]
VSS cnt_reg[23]
VDD cnt_reg[23]
VSS cnt_reg[22]
VDD cnt_reg[22]
VSS cnt_reg[21]
VDD cnt_reg[21]
VSS cnt_reg[20]
VDD cnt_reg[20]
VSS cnt_reg[1]
VDD cnt_reg[1]
VSS cnt_reg[19]
VDD cnt_reg[19]
VSS cnt_reg[18]
VDD cnt_reg[18]
VSS cnt_reg[17]
VDD cnt_reg[17]
VSS cnt_reg[16]
VDD cnt_reg[16]
VSS cnt_reg[15]
VDD cnt_reg[15]
VSS cnt_reg[14]
VDD cnt_reg[14]
VSS cnt_reg[13]
VDD cnt_reg[13]
VSS cnt_reg[12]
VDD cnt_reg[12]
VSS cnt_reg[11]
VDD cnt_reg[11]
VSS g92
VDD g92
VSS g91
VDD g91
VSS pwm_cnt_reg[1]
VDD pwm_cnt_reg[1]
VSS g89
VDD g89
VSS g88
VDD g88
VSS pwm_cnt_reg[2]
VDD pwm_cnt_reg[2]
VSS g86
VDD g86
VSS pwm_cnt_reg[3]
VDD pwm_cnt_reg[3]
VSS g259
VDD g259
VSS g258
VDD g258
VSS g257
VDD g257
VSS g256
VDD g256
VSS g255
VDD g255
VSS g254
VDD g254
VSS g253
VDD g253
VSS g252
VDD g252
VSS g251
VDD g251
VSS g250
VDD g250
VSS g249
VDD g249
VSS g248
VDD g248
VSS inc_add_12_12_1/g256
VDD inc_add_12_12_1/g256
VSS inc_add_12_12_1/g255
VDD inc_add_12_12_1/g255
VSS inc_add_12_12_1/g254
VDD inc_add_12_12_1/g254
VSS inc_add_12_12_1/g253
VDD inc_add_12_12_1/g253
VSS inc_add_12_12_1/g252
VDD inc_add_12_12_1/g252
VSS inc_add_12_12_1/g251
VDD inc_add_12_12_1/g251
VSS inc_add_12_12_1/g250
VDD inc_add_12_12_1/g250
VSS inc_add_12_12_1/g249
VDD inc_add_12_12_1/g249
VSS inc_add_12_12_1/g248
VDD inc_add_12_12_1/g248
VSS inc_add_12_12_1/g247
VDD inc_add_12_12_1/g247
VSS inc_add_12_12_1/g246
VDD inc_add_12_12_1/g246
VSS inc_add_12_12_1/g245
VDD inc_add_12_12_1/g245
VSS inc_add_12_12_1/g244
VDD inc_add_12_12_1/g244
VSS inc_add_12_12_1/g243
VDD inc_add_12_12_1/g243
VSS inc_add_12_12_1/g242
VDD inc_add_12_12_1/g242
VSS inc_add_12_12_1/g241
VDD inc_add_12_12_1/g241
VSS inc_add_12_12_1/g240
VDD inc_add_12_12_1/g240
VSS inc_add_12_12_1/g239
VDD inc_add_12_12_1/g239
VSS inc_add_12_12_1/g238
VDD inc_add_12_12_1/g238
VSS inc_add_12_12_1/g237
VDD inc_add_12_12_1/g237
VSS inc_add_12_12_1/g236
VDD inc_add_12_12_1/g236
VSS inc_add_12_12_1/g235
VDD inc_add_12_12_1/g235
VSS inc_add_12_12_1/g234
VDD inc_add_12_12_1/g234
VSS inc_add_12_12_1/g233
VDD inc_add_12_12_1/g233
VSS inc_add_12_12_1/g232
VDD inc_add_12_12_1/g232
VSS inc_add_12_12_1/g231
VDD inc_add_12_12_1/g231
VSS inc_add_12_12_1/g230
VDD inc_add_12_12_1/g230
VSS inc_add_12_12_1/g229
VDD inc_add_12_12_1/g229
VSS inc_add_12_12_1/g228
VDD inc_add_12_12_1/g228
VSS inc_add_12_12_1/g227
VDD inc_add_12_12_1/g227
VSS inc_add_12_12_1/g226
VDD inc_add_12_12_1/g226
VSS inc_add_12_12_1/g225
VDD inc_add_12_12_1/g225
VSS inc_add_12_12_1/g224
VDD inc_add_12_12_1/g224
VSS inc_add_12_12_1/g223
VDD inc_add_12_12_1/g223
VSS inc_add_12_12_1/g222
VDD inc_add_12_12_1/g222
VSS inc_add_12_12_1/g221
VDD inc_add_12_12_1/g221
VSS inc_add_12_12_1/g220
VDD inc_add_12_12_1/g220
VSS inc_add_12_12_1/g219
VDD inc_add_12_12_1/g219
VSS inc_add_12_12_1/g218
VDD inc_add_12_12_1/g218
VSS inc_add_12_12_1/g217
VDD inc_add_12_12_1/g217
VSS inc_add_12_12_1/g216
VDD inc_add_12_12_1/g216
VSS inc_add_12_12_1/g215
VDD inc_add_12_12_1/g215
VSS inc_add_12_12_1/g214
VDD inc_add_12_12_1/g214
VSS inc_add_12_12_1/g213
VDD inc_add_12_12_1/g213
VSS inc_add_12_12_1/g212
VDD inc_add_12_12_1/g212
VSS inc_add_12_12_1/g211
VDD inc_add_12_12_1/g211
VSS inc_add_12_12_1/g210
VDD inc_add_12_12_1/g210
VSS inc_add_12_12_1/g209
VDD inc_add_12_12_1/g209
VSS inc_add_12_12_1/g208
VDD inc_add_12_12_1/g208
VSS inc_add_12_12_1/g207
VDD inc_add_12_12_1/g207
VSS inc_add_12_12_1/g206
VDD inc_add_12_12_1/g206
VSS inc_add_12_12_1/g205
VDD inc_add_12_12_1/g205
VSS inc_add_12_12_1/g204
VDD inc_add_12_12_1/g204
VSS inc_add_12_12_1/g203
VDD inc_add_12_12_1/g203
VSS inc_add_12_12_1/g202
VDD inc_add_12_12_1/g202
VSS inc_add_12_12_1/g201
VDD inc_add_12_12_1/g201
VSS inc_add_12_12_1/g200
VDD inc_add_12_12_1/g200
VSS inc_add_12_12_1/g199
VDD inc_add_12_12_1/g199
VSS inc_add_12_12_1/g198
VDD inc_add_12_12_1/g198
VSS inc_add_12_12_1/g197
VDD inc_add_12_12_1/g197
VSS inc_add_12_12_1/g196
VDD inc_add_12_12_1/g196
VSS inc_add_12_12_1/g195
VDD inc_add_12_12_1/g195
VSS inc_add_12_12_1/g194
VDD inc_add_12_12_1/g194
VSS inc_add_12_12_1/g193
VDD inc_add_12_12_1/g193
VSS inc_add_12_12_1/g192
VDD inc_add_12_12_1/g192
VSS inc_add_12_12_1/g191
VDD inc_add_12_12_1/g191
VSS inc_add_12_12_1/g190
VDD inc_add_12_12_1/g190
VSS inc_add_12_12_1/g189
VDD inc_add_12_12_1/g189
VSS inc_add_12_12_1/g188
VDD inc_add_12_12_1/g188
VSS inc_add_12_12_1/g187
VDD inc_add_12_12_1/g187
VSS inc_add_12_12_1/g186
VDD inc_add_12_12_1/g186
VSS inc_add_12_12_1/g185
VDD inc_add_12_12_1/g185
VSS inc_add_12_12_1/g184
VDD inc_add_12_12_1/g184
VSS inc_add_12_12_1/g183
VDD inc_add_12_12_1/g183
VSS inc_add_12_12_1/g182
VDD inc_add_12_12_1/g182 306
# PG Pins Connect to Non-PG Net 0
# Power Pins Connect Ground Net 0
# Ground Pins Connect Power Net 0 306
Average Pins Per Net(Signal): 2.497
==============================
General Library Information
==============================
# Routing Layers: 10
# Masterslice Layers: 2
# Pin Layers:
General Caution:
1) Library have metal1, metal2 and metal3 pins, you should setPreRouteAsObs {1 2 3} to ensure these pins are accessible after placement
------------------------------
Pin Layers
------------------------------
metal3
metal2
metal1 3
# Layers:
------------------------------
Layer OVERLAP Information
------------------------------
Type Overlap
------------------------------
Layer metal10 Information
------------------------------
Type Routing
Wire Pitch X 1.600 um
Wire Pitch Y 1.600 um
Offset X 0.095 um
Offset Y 0.070 um
Wire Width 0.800 um
Spacing 0.800 um
------------------------------
Layer via9 Information
------------------------------
Type Cut
Wire Width 0.800 um
Vias
------------------------------
Via list in layer via9
------------------------------
Vias in via9 Default
via9_0 Yes For complete list click here
Multiple Orientation Vias CAUTION: There is only one default via in this layer
------------------------------
Layer metal9 Information
------------------------------
Type Routing
Wire Pitch X 1.600 um
Wire Pitch Y 1.600 um
Offset X 0.095 um
Offset Y 0.070 um
Wire Width 0.800 um
Spacing 0.800 um
------------------------------
Layer via8 Information
------------------------------
Type Cut
Wire Width 0.400 um
Vias
------------------------------
Via list in layer via8
------------------------------
Vias in via8 Default
via8_0 Yes For complete list click here
Multiple Orientation Vias CAUTION: There is only one default via in this layer
------------------------------
Layer metal8 Information
------------------------------
Type Routing
Wire Pitch X 0.800 um
Wire Pitch Y 0.800 um
Offset X 0.095 um
Offset Y 0.070 um
Wire Width 0.400 um
Spacing 0.400 um
------------------------------
Layer via7 Information
------------------------------
Type Cut
Wire Width 0.400 um
Vias
------------------------------
Via list in layer via7
------------------------------
Vias in via7 Default
via7_0 Yes For complete list click here
Multiple Orientation Vias CAUTION: There is only one default via in this layer
------------------------------
Layer metal7 Information
------------------------------
Type Routing
Wire Pitch X 0.800 um
Wire Pitch Y 0.800 um
Offset X 0.095 um
Offset Y 0.070 um
Wire Width 0.400 um
Spacing 0.400 um
------------------------------
Layer via6 Information
------------------------------
Type Cut
Wire Width 0.140 um
Vias
------------------------------
Via list in layer via6
------------------------------
Vias in via6 Default
via6_0 Yes For complete list click here
Multiple Orientation Vias CAUTION: There is only one default via in this layer
------------------------------
Layer metal6 Information
------------------------------
Type Routing
Wire Pitch X 0.280 um
Wire Pitch Y 0.280 um
Offset X 0.095 um
Offset Y 0.070 um
Wire Width 0.140 um
Spacing 0.140 um
------------------------------
Layer via5 Information
------------------------------
Type Cut
Wire Width 0.140 um
Vias
------------------------------
Via list in layer via5
------------------------------
Vias in via5 Default
via5_0 Yes For complete list click here
Multiple Orientation Vias CAUTION: There is only one default via in this layer
------------------------------
Layer metal5 Information
------------------------------
Type Routing
Wire Pitch X 0.280 um
Wire Pitch Y 0.280 um
Offset X 0.095 um
Offset Y 0.070 um
Wire Width 0.140 um
Spacing 0.140 um
------------------------------
Layer via4 Information
------------------------------
Type Cut
Wire Width 0.140 um
Vias
------------------------------
Via list in layer via4
------------------------------
Vias in via4 Default
via4_0 Yes For complete list click here
Multiple Orientation Vias CAUTION: There is only one default via in this layer
------------------------------
Layer metal4 Information
------------------------------
Type Routing
Wire Pitch X 0.280 um
Wire Pitch Y 0.280 um
Offset X 0.095 um
Offset Y 0.070 um
Wire Width 0.140 um
Spacing 0.140 um
------------------------------
Layer via3 Information
------------------------------
Type Cut
Wire Width 0.070 um
Vias
------------------------------
Via list in layer via3
------------------------------
Vias in via3 Default
via3_1 Yes
via3_0 Yes
via3_2 Yes For complete list click here
------------------------------
Layer metal3 Information
------------------------------
Type Routing
Wire Pitch X 0.140 um
Wire Pitch Y 0.140 um
Offset X 0.095 um
Offset Y 0.070 um
Wire Width 0.070 um
Spacing 0.070 um
------------------------------
Layer via2 Information
------------------------------
Type Cut
Wire Width 0.070 um
Vias
------------------------------
Via list in layer via2
------------------------------
Vias in via2 Default
via2_3 Yes
via2_2 Yes
via2_1 Yes
via2_0 Yes
via2_6 Yes
via2_7 Yes
via2_5 Yes
via2_4 Yes
via2_8 Yes For complete list click here
------------------------------
Layer metal2 Information
------------------------------
Type Routing
Wire Pitch X 0.190 um
Wire Pitch Y 0.190 um
Offset X 0.095 um
Offset Y 0.070 um
Wire Width 0.070 um
Spacing 0.070 um
------------------------------
Layer via1 Information
------------------------------
Type Cut
Wire Width 0.070 um
Vias
------------------------------
Via list in layer via1
------------------------------
Vias in via1 Default
via1_8 Yes
via1_7 Yes
via1_6 Yes
via1_5 Yes
via1_3 Yes
via1_2 Yes
via1_1 Yes
via1_0 Yes
via1_4 Yes For complete list click here
------------------------------
Layer metal1 Information
------------------------------
Type Routing
Wire Pitch X 0.140 um
Wire Pitch Y 0.140 um
Offset X 0.095 um
Offset Y 0.070 um
Wire Width 0.070 um
Spacing 0.065 um
------------------------------
Layer active Information
------------------------------
Type Masterslice
------------------------------
Layer poly Information
------------------------------
Type Masterslice 22
# Pins without Physical Port: 0
# Pins in Library without Timing Lib: 0
# Pins Missing Direction: 0
Antenna Summary Report:
General Caution:
1) All Antenna Constructs are absent for the layer section of LEF.
------------------------------
These Pins have antenna info
------------------------------
Cell Name List of Pin Name
AND2_X1 A1
AND2_X1 A2
AND2_X1 ZN
AND2_X2 A1
AND2_X2 A2
AND2_X2 ZN
AND2_X4 A1
AND2_X4 A2
AND2_X4 ZN
AND3_X1 A1
AND3_X1 A2
AND3_X1 A3
AND3_X1 ZN
AND3_X2 A1
AND3_X2 A2
AND3_X2 A3
AND3_X2 ZN
AND3_X4 A1
AND3_X4 A2
AND3_X4 A3
AND3_X4 ZN
AND4_X1 A1
AND4_X1 A2
AND4_X1 A3
AND4_X1 A4
AND4_X1 ZN
AND4_X2 A1
AND4_X2 A2
AND4_X2 A3
AND4_X2 A4
AND4_X2 ZN
AND4_X4 A1
AND4_X4 A2
AND4_X4 A3
AND4_X4 A4
AND4_X4 ZN
ANTENNA_X1 A
AOI211_X1 A
AOI211_X1 B
AOI211_X1 C1
AOI211_X1 C2
AOI211_X1 ZN
AOI211_X2 A
AOI211_X2 B
AOI211_X2 C1
AOI211_X2 C2
AOI211_X2 ZN
AOI211_X4 A
AOI211_X4 B
AOI211_X4 C1
AOI211_X4 C2
AOI211_X4 ZN
AOI21_X1 A
AOI21_X1 B1
AOI21_X1 B2
AOI21_X1 ZN
AOI21_X2 A
AOI21_X2 B1
AOI21_X2 B2
AOI21_X2 ZN
AOI21_X4 A
AOI21_X4 B1
AOI21_X4 B2
AOI21_X4 ZN
AOI221_X1 A
AOI221_X1 B1
AOI221_X1 B2
AOI221_X1 C1
AOI221_X1 C2
AOI221_X1 ZN
AOI221_X2 A
AOI221_X2 B1
AOI221_X2 B2
AOI221_X2 C1
AOI221_X2 C2
AOI221_X2 ZN
AOI221_X4 A
AOI221_X4 B1
AOI221_X4 B2
AOI221_X4 C1
AOI221_X4 C2
AOI221_X4 ZN
AOI222_X1 A1
AOI222_X1 A2
AOI222_X1 B1
AOI222_X1 B2
AOI222_X1 C1
AOI222_X1 C2
AOI222_X1 ZN
AOI222_X2 A1
AOI222_X2 A2
AOI222_X2 B1
AOI222_X2 B2
AOI222_X2 C1
AOI222_X2 C2
AOI222_X2 ZN
AOI222_X4 A1
AOI222_X4 A2
AOI222_X4 B1
AOI222_X4 B2
AOI222_X4 C1
AOI222_X4 C2
AOI222_X4 ZN
AOI22_X1 A1
AOI22_X1 A2
AOI22_X1 B1
AOI22_X1 B2
AOI22_X1 ZN
AOI22_X2 A1
AOI22_X2 A2
AOI22_X2 B1
AOI22_X2 B2
AOI22_X2 ZN
AOI22_X4 A1
AOI22_X4 A2
AOI22_X4 B1
AOI22_X4 B2
AOI22_X4 ZN
BUF_X1 A
BUF_X1 Z
BUF_X16 A
BUF_X16 Z
BUF_X2 A
BUF_X2 Z
BUF_X32 A
BUF_X32 Z
BUF_X4 A
BUF_X4 Z
BUF_X8 A
BUF_X8 Z
CLKBUF_X1 A
CLKBUF_X1 Z
CLKBUF_X2 A
CLKBUF_X2 Z
CLKBUF_X3 A
CLKBUF_X3 Z
CLKGATETST_X1 CK
CLKGATETST_X1 E
CLKGATETST_X1 GCK
CLKGATETST_X1 SE
CLKGATETST_X2 CK
CLKGATETST_X2 E
CLKGATETST_X2 GCK
CLKGATETST_X2 SE
CLKGATETST_X4 CK
CLKGATETST_X4 E
CLKGATETST_X4 GCK
CLKGATETST_X4 SE
CLKGATETST_X8 CK
CLKGATETST_X8 E
CLKGATETST_X8 GCK
CLKGATETST_X8 SE
CLKGATE_X1 CK
CLKGATE_X1 E
CLKGATE_X1 GCK
CLKGATE_X2 CK
CLKGATE_X2 E
CLKGATE_X2 GCK
CLKGATE_X4 CK
CLKGATE_X4 E
CLKGATE_X4 GCK
CLKGATE_X8 CK
CLKGATE_X8 E
CLKGATE_X8 GCK
DFFRS_X1 CK
DFFRS_X1 D
DFFRS_X1 Q
DFFRS_X1 QN
DFFRS_X1 RN
DFFRS_X1 SN
DFFRS_X2 CK
DFFRS_X2 D
DFFRS_X2 Q
DFFRS_X2 QN
DFFRS_X2 RN
DFFRS_X2 SN
DFFR_X1 CK
DFFR_X1 D
DFFR_X1 Q
DFFR_X1 QN
DFFR_X1 RN
DFFR_X2 CK
DFFR_X2 D
DFFR_X2 Q
DFFR_X2 QN
DFFR_X2 RN
DFFS_X1 CK
DFFS_X1 D
DFFS_X1 Q
DFFS_X1 QN
DFFS_X1 SN
DFFS_X2 CK
DFFS_X2 D
DFFS_X2 Q
DFFS_X2 QN
DFFS_X2 SN
DFF_X1 CK
DFF_X1 D
DFF_X1 Q
DFF_X1 QN
DFF_X2 CK
DFF_X2 D
DFF_X2 Q
DFF_X2 QN
DLH_X1 D
DLH_X1 G
DLH_X1 Q
DLH_X2 D
DLH_X2 G
DLH_X2 Q
DLL_X1 D
DLL_X1 GN
DLL_X1 Q
DLL_X2 D
DLL_X2 GN
DLL_X2 Q
FA_X1 A
FA_X1 B
FA_X1 CI
FA_X1 CO
FA_X1 S
HA_X1 A
HA_X1 B
HA_X1 CO
HA_X1 S
INV_X1 A
INV_X1 ZN
INV_X16 A
INV_X16 ZN
INV_X2 A
INV_X2 ZN
INV_X32 A
INV_X32 ZN
INV_X4 A
INV_X4 ZN
INV_X8 A
INV_X8 ZN
LOGIC0_X1 Z
LOGIC1_X1 Z
MUX2_X1 A
MUX2_X1 B
MUX2_X1 S
MUX2_X1 Z
MUX2_X2 A
MUX2_X2 B
MUX2_X2 S
MUX2_X2 Z
NAND2_X1 A1
NAND2_X1 A2
NAND2_X1 ZN
NAND2_X2 A1
NAND2_X2 A2
NAND2_X2 ZN
NAND2_X4 A1
NAND2_X4 A2
NAND2_X4 ZN
NAND3_X1 A1
NAND3_X1 A2
NAND3_X1 A3
NAND3_X1 ZN
NAND3_X2 A1
NAND3_X2 A2
NAND3_X2 A3
NAND3_X2 ZN
NAND3_X4 A1
NAND3_X4 A2
NAND3_X4 A3
NAND3_X4 ZN
NAND4_X1 A1
NAND4_X1 A2
NAND4_X1 A3
NAND4_X1 A4
NAND4_X1 ZN
NAND4_X2 A1
NAND4_X2 A2
NAND4_X2 A3
NAND4_X2 A4
NAND4_X2 ZN
NAND4_X4 A1
NAND4_X4 A2
NAND4_X4 A3
NAND4_X4 A4
NAND4_X4 ZN
NOR2_X1 A1
NOR2_X1 A2
NOR2_X1 ZN
NOR2_X2 A1
NOR2_X2 A2
NOR2_X2 ZN
NOR2_X4 A1
NOR2_X4 A2
NOR2_X4 ZN
NOR3_X1 A1
NOR3_X1 A2
NOR3_X1 A3
NOR3_X1 ZN
NOR3_X2 A1
NOR3_X2 A2
NOR3_X2 A3
NOR3_X2 ZN
NOR3_X4 A1
NOR3_X4 A2
NOR3_X4 A3
NOR3_X4 ZN
NOR4_X1 A1
NOR4_X1 A2
NOR4_X1 A3
NOR4_X1 A4
NOR4_X1 ZN
NOR4_X2 A1
NOR4_X2 A2
NOR4_X2 A3
NOR4_X2 A4
NOR4_X2 ZN
NOR4_X4 A1
NOR4_X4 A2
NOR4_X4 A3
NOR4_X4 A4
NOR4_X4 ZN
OAI211_X1 A
OAI211_X1 B
OAI211_X1 C1
OAI211_X1 C2
OAI211_X1 ZN
OAI211_X2 A
OAI211_X2 B
OAI211_X2 C1
OAI211_X2 C2
OAI211_X2 ZN
OAI211_X4 A
OAI211_X4 B
OAI211_X4 C1
OAI211_X4 C2
OAI211_X4 ZN
OAI21_X1 A
OAI21_X1 B1
OAI21_X1 B2
OAI21_X1 ZN
OAI21_X2 A
OAI21_X2 B1
OAI21_X2 B2
OAI21_X2 ZN
OAI21_X4 A
OAI21_X4 B1
OAI21_X4 B2
OAI21_X4 ZN
OAI221_X1 A
OAI221_X1 B1
OAI221_X1 B2
OAI221_X1 C1
OAI221_X1 C2
OAI221_X1 ZN
OAI221_X2 A
OAI221_X2 B1
OAI221_X2 B2
OAI221_X2 C1
OAI221_X2 C2
OAI221_X2 ZN
OAI221_X4 A
OAI221_X4 B1
OAI221_X4 B2