@@ -1662,21 +1662,22 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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module ->memories [memory->name ] = memory;
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import_attributes (memory->attributes , net, nl);
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- int number_of_bits = net->Size ();
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- int bits_in_word = number_of_bits;
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+ uint64_t number_of_bits = net->Size ();
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+ uint64_t bits_in_word = number_of_bits;
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FOREACH_PORTREF_OF_NET (net, si, pr) {
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if (pr->GetInst ()->Type () == OPER_READ_PORT) {
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- bits_in_word = min<int >(bits_in_word, pr->GetInst ()->OutputSize ());
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+ bits_in_word = min<uint64_t >(bits_in_word, pr->GetInst ()->OutputSize ());
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continue ;
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}
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if (pr->GetInst ()->Type () == OPER_WRITE_PORT || pr->GetInst ()->Type () == OPER_CLOCKED_WRITE_PORT) {
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- bits_in_word = min<int >(bits_in_word, pr->GetInst ()->Input2Size ());
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+ bits_in_word = min<uint64_t >(bits_in_word, pr->GetInst ()->Input2Size ());
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continue ;
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}
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log_error (" Verific RamNet %s is connected to unsupported instance type %s (%s).\n " ,
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net->Name (), pr->GetInst ()->View ()->Owner ()->Name (), pr->GetInst ()->Name ());
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}
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-
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+ if ((bits_in_word * number_of_bits) > (1 << 23 ))
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+ log_error (" Memory %s size is larger than 2**23 bits\n " , net->Name ());
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memory->width = bits_in_word;
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memory->size = number_of_bits / bits_in_word;
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