Merge branch 'privileged1.10' of ssh://github.com/RoaLogic/RV12 into RC/v1.3-rc2

Author: sphardy

bench/verilog/ahb3lite/testbench_top.sv

@@ -42,12 +42,12 @@ module testbench_top;
 
 //core parameters
 parameter XLEN             = 64;
-parameter PHYS_ADDR_SIZE   = 32;           //32bit address bus. Also sets non-cacheable range
+parameter PLEN             = XLEN;         //32bit address bus
 parameter PC_INIT          = 'h8000_0000;  //Start here after reset
 parameter BASE             = PC_INIT;      //offset where to load program in memory
 parameter INIT_FILE        = "test.hex";
 parameter MEM_LATENCY      = 1;
-parameter WRITEBUFFER_SIZE = 8;
+parameter WRITEBUFFER_SIZE = 4;
 parameter HAS_U            = 1;
 parameter HAS_S            = 1;
 parameter HAS_H            = 0;
@@ -81,66 +81,66 @@ localparam MULLAT = MULT_LATENCY > 4 ? 4 : MULT_LATENCY;
 //
 // Variables
 //
-logic                      HCLK, HRESETn;
+logic            HCLK, HRESETn;
 
 //Instruction interface
-logic                      ins_HSEL;
-logic [PHYS_ADDR_SIZE-1:0] ins_HADDR;
-logic [XLEN          -1:0] ins_HRDATA;
-logic [XLEN          -1:0] ins_HWDATA; //always 0
-logic                      ins_HWRITE; //always 0
-logic [               2:0] ins_HSIZE;
-logic [               2:0] ins_HBURST;
-logic [               3:0] ins_HPROT;
-logic [               1:0] ins_HTRANS;
-logic                      ins_HMASTLOCK;
-logic                      ins_HREADY;
-logic                      ins_HRESP;
+logic            ins_HSEL;
+logic [PLEN-1:0] ins_HADDR;
+logic [XLEN-1:0] ins_HRDATA;
+logic [XLEN-1:0] ins_HWDATA; //always 0
+logic            ins_HWRITE; //always 0
+logic [     2:0] ins_HSIZE;
+logic [     2:0] ins_HBURST;
+logic [     3:0] ins_HPROT;
+logic [     1:0] ins_HTRANS;
+logic            ins_HMASTLOCK;
+logic            ins_HREADY;
+logic            ins_HRESP;
 
 //Data interface
-logic                      dat_HSEL;
-logic [PHYS_ADDR_SIZE-1:0] dat_HADDR;
-logic [XLEN          -1:0] dat_HWDATA;
-logic [XLEN          -1:0] dat_HRDATA;
-logic                      dat_HWRITE;
-logic [               2:0] dat_HSIZE;
-logic [               2:0] dat_HBURST;
-logic [               3:0] dat_HPROT;
-logic [               1:0] dat_HTRANS;
-logic                      dat_HMASTLOCK;
-logic                      dat_HREADY;
-logic                      dat_HRESP;
+logic            dat_HSEL;
+logic [PLEN-1:0] dat_HADDR;
+logic [XLEN-1:0] dat_HWDATA;
+logic [XLEN-1:0] dat_HRDATA;
+logic            dat_HWRITE;
+logic [     2:0] dat_HSIZE;
+logic [     2:0] dat_HBURST;
+logic [     3:0] dat_HPROT;
+logic [     1:0] dat_HTRANS;
+logic            dat_HMASTLOCK;
+logic            dat_HREADY;
+logic            dat_HRESP;
 
 //Debug Interface
-logic              dbp_bp,
-                   dbg_stall,
-                   dbg_strb,
-                   dbg_ack,
-                   dbg_we;
-logic [      15:0] dbg_addr;
-logic [XLEN  -1:0] dbg_dati,
-                   dbg_dato;
+logic            dbp_bp,
+                 dbg_stall,
+                 dbg_strb,
+                 dbg_ack,
+                 dbg_we;
+logic [    15:0] dbg_addr;
+logic [XLEN-1:0] dbg_dati,
+                 dbg_dato;
 
 
 
 //Host Interface
-logic                      host_csr_req,
-                           host_csr_ack,
-                           host_csr_we;
-logic [XLEN          -1:0] host_csr_tohost,
-                           host_csr_fromhost;
+logic            host_csr_req,
+                 host_csr_ack,
+                 host_csr_we;
+logic [XLEN-1:0] host_csr_tohost,
+                 host_csr_fromhost;
 
 
 //Unified memory interface
-logic [               1:0] mem_htrans[2];
-logic [               3:0] mem_hburst[2];
-logic                      mem_hready[2],
-                           mem_hresp[2];
-logic [PHYS_ADDR_SIZE-1:0] mem_haddr[2];
-logic [XLEN          -1:0] mem_hwdata[2],
-                           mem_hrdata[2];
-logic [               2:0] mem_hsize[2];
-logic                      mem_hwrite[2];
+logic [     1:0] mem_htrans[2];
+logic [     3:0] mem_hburst[2];
+logic            mem_hready[2],
+                 mem_hresp[2];
+logic [PLEN-1:0] mem_haddr[2];
+logic [XLEN-1:0] mem_hwdata[2],
+                 mem_hrdata[2];
+logic [     2:0] mem_hsize[2];
+logic            mem_hwrite[2];
 
 
 ////////////////////////////////////////////////////////////////
@@ -152,7 +152,7 @@ logic                      mem_hwrite[2];
 
 riscv_top_ahb3lite #(
   .XLEN             ( XLEN             ),
-  .PHYS_ADDR_SIZE   ( PHYS_ADDR_SIZE   ), //31bit address bus
+  .PLEN             ( PLEN             ), //31bit address bus
   .PC_INIT          ( PC_INIT          ),
   .HAS_USER         ( HAS_U            ),
   .HAS_SUPER        ( HAS_S            ),
@@ -221,11 +221,11 @@ assign dat_HRESP     = mem_hresp[1];
 
 //hookup memory model
 memory_model_ahb3lite #(
-  .DATA_WIDTH ( XLEN           ),
-  .ADDR_WIDTH ( PHYS_ADDR_SIZE ),
-  .BASE       ( BASE           ),
-  .PORTS      (              2 ),
-  .LATENCY    ( MEM_LATENCY    ) )
+  .DATA_WIDTH ( XLEN        ),
+  .ADDR_WIDTH ( PLEN        ),
+  .BASE       ( BASE        ),
+  .PORTS      (           2 ),
+  .LATENCY    ( MEM_LATENCY ) )
 unified_memory (
   .HRESETn ( HRESETn ),
   .HCLK   ( HCLK       ),
@@ -258,7 +258,7 @@ generate
   else
   begin
       //New MMIO interface
-      mmio_if #(XLEN, PHYS_ADDR_SIZE, TOHOST, UART_TX)
+      mmio_if #(XLEN, PLEN, TOHOST, UART_TX)
       mmio_if_inst (
         .HRESETn ( HRESETn ),
         .HCLK    ( HCLK    ),