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| 1 | +/* |
| 2 | + * Copyright (c) 2006-2025, RT-Thread Development Team |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | + |
| 7 | +#include <rtdevice.h> |
| 8 | +#include "board.h" |
| 9 | +#include "drv_adc.h" |
| 10 | +#include <hal_gpio.h> |
| 11 | +#include <hal_adc.h> |
| 12 | +#include <hal_rcc.h> |
| 13 | +#include <hal_misc.h> |
| 14 | + |
| 15 | +#if defined(BSP_USING_ADC) |
| 16 | + |
| 17 | +#define LOG_TAG "drv.adc" |
| 18 | +#include <rtdbg.h> |
| 19 | + |
| 20 | +#if defined(SOC_SERIES_MM32F327) |
| 21 | +#define ADC_CONFIG_GPIORCC RCC_AHBENR_GPIOA |
| 22 | +#define ADC_CONFIG_GPIOX GPIOA |
| 23 | +#define ADC_CONFIG_IOX (GPIO_Pin_5 | GPIO_Pin_4) |
| 24 | +#endif |
| 25 | + |
| 26 | +struct mm32_adc |
| 27 | +{ |
| 28 | + struct rt_adc_device device; |
| 29 | + ADC_TypeDef *instance; |
| 30 | + const char *name; |
| 31 | +}; |
| 32 | + |
| 33 | +static struct mm32_adc adc_obj[] = |
| 34 | +{ |
| 35 | +#if defined(BSP_USING_ADC1) |
| 36 | + { |
| 37 | + .instance = ADC1, |
| 38 | + .name = "adc1", |
| 39 | + }, |
| 40 | +#endif |
| 41 | +#if defined(BSP_USING_ADC2) |
| 42 | + { |
| 43 | + .instance = ADC2, |
| 44 | + .name = "adc2", |
| 45 | + }, |
| 46 | +#endif |
| 47 | +}; |
| 48 | + |
| 49 | +static void mm32_adc_channel_enable(ADC_TypeDef *adc, rt_uint32_t channel) |
| 50 | +{ |
| 51 | +#if defined(SOC_SERIES_MM32F526) |
| 52 | + adc->ADCHS &= ~(1UL << channel); |
| 53 | + adc->ADCHS |= (1UL << channel); |
| 54 | +#elif defined(SOC_SERIES_MM32F327) |
| 55 | + adc->CHSR &= ~(1UL << channel); |
| 56 | + adc->CHSR |= (1UL << channel); |
| 57 | +#else |
| 58 | +#error "Unsupported MM32 ADC series" |
| 59 | +#endif |
| 60 | +} |
| 61 | + |
| 62 | +static void mm32_adc_clock_enable(ADC_TypeDef *adc, rt_bool_t enabled) |
| 63 | +{ |
| 64 | +#if defined(SOC_SERIES_MM32F526) |
| 65 | + if (adc == ADC1) |
| 66 | + { |
| 67 | + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, enabled ? ENABLE : DISABLE); |
| 68 | + } |
| 69 | +#ifdef ADC2 |
| 70 | + else if (adc == ADC2) |
| 71 | + { |
| 72 | + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC2, enabled ? ENABLE : DISABLE); |
| 73 | + } |
| 74 | +#endif |
| 75 | +#elif defined(SOC_SERIES_MM32F327) |
| 76 | + if (adc == ADC1) |
| 77 | + { |
| 78 | + RCC_APB2PeriphClockCmd(RCC_APB2ENR_ADC1, enabled ? ENABLE : DISABLE); |
| 79 | + } |
| 80 | +#ifdef ADC2 |
| 81 | + else if (adc == ADC2) |
| 82 | + { |
| 83 | + RCC_APB2PeriphClockCmd(RCC_APB2ENR_ADC2, enabled ? ENABLE : DISABLE); |
| 84 | + } |
| 85 | +#endif |
| 86 | +#endif |
| 87 | +} |
| 88 | + |
| 89 | +static void mm32_adc_hw_config(ADC_TypeDef *adc, rt_uint32_t channel) |
| 90 | +{ |
| 91 | + ADC_InitTypeDef init; |
| 92 | +#if defined(SOC_SERIES_MM32F327) |
| 93 | + GPIO_InitTypeDef gpio_init; |
| 94 | +#endif |
| 95 | + |
| 96 | +#if defined(SOC_SERIES_MM32F526) |
| 97 | + mm32_msp_adc_init((void *)adc); |
| 98 | + ADC_CalibrationConfig(adc, 0x1FE); |
| 99 | +#else |
| 100 | + mm32_adc_clock_enable(adc, RT_TRUE); |
| 101 | +#endif |
| 102 | + |
| 103 | + ADC_StructInit(&init); |
| 104 | + init.ADC_Resolution = ADC_Resolution_12b; |
| 105 | + init.ADC_DataAlign = ADC_DataAlign_Right; |
| 106 | + |
| 107 | +#if defined(SOC_SERIES_MM32F526) |
| 108 | + init.ADC_Prescaler = ADC_Prescaler_16; |
| 109 | + init.ADC_Mode = ADC_Mode_Scan; |
| 110 | + ADC_Init(adc, &init); |
| 111 | + ADC_SampleTimeConfig(adc, channel, ADC_SampleTime_240_5); |
| 112 | + ADC_ChannelCmd(adc, channel, ENABLE); |
| 113 | + ADC_DifferentialConversionConfig(adc, ADC_Pseudo_Differential_Conversion_4_5); |
| 114 | +#elif defined(SOC_SERIES_MM32F327) |
| 115 | + init.ADC_PRESCARE = ADC_PCLK2_PRESCARE_16; |
| 116 | + init.ADC_Mode = ADC_Mode_Continue; |
| 117 | + init.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; |
| 118 | + ADC_Init(adc, &init); |
| 119 | + ADC_RegularChannelConfig(adc, channel, 0, ADC_Samctl_239_5); |
| 120 | + |
| 121 | + GPIO_StructInit(&gpio_init); |
| 122 | + RCC_AHBPeriphClockCmd(ADC_CONFIG_GPIORCC, ENABLE); |
| 123 | + gpio_init.GPIO_Pin = ADC_CONFIG_IOX; |
| 124 | + gpio_init.GPIO_Speed = GPIO_Speed_50MHz; |
| 125 | + gpio_init.GPIO_Mode = GPIO_Mode_AIN; |
| 126 | + GPIO_Init(ADC_CONFIG_GPIOX, &gpio_init); |
| 127 | +#endif |
| 128 | + |
| 129 | + ADC_Cmd(adc, ENABLE); |
| 130 | + mm32_adc_channel_enable(adc, channel); |
| 131 | +} |
| 132 | + |
| 133 | +static rt_err_t mm32_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled) |
| 134 | +{ |
| 135 | + ADC_TypeDef *adc; |
| 136 | + |
| 137 | + RT_ASSERT(device != RT_NULL); |
| 138 | + adc = device->parent.user_data; |
| 139 | + |
| 140 | + if (enabled) |
| 141 | + { |
| 142 | + mm32_adc_hw_config(adc, (rt_uint32_t)channel); |
| 143 | + } |
| 144 | + else |
| 145 | + { |
| 146 | + ADC_DeInit(adc); |
| 147 | + ADC_Cmd(adc, DISABLE); |
| 148 | + mm32_adc_clock_enable(adc, RT_FALSE); |
| 149 | + } |
| 150 | + |
| 151 | + return RT_EOK; |
| 152 | +} |
| 153 | + |
| 154 | +static rt_err_t mm32_adc_get_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value) |
| 155 | +{ |
| 156 | + ADC_TypeDef *adc; |
| 157 | + |
| 158 | + RT_ASSERT(device != RT_NULL); |
| 159 | + RT_ASSERT(value != RT_NULL); |
| 160 | + adc = device->parent.user_data; |
| 161 | + |
| 162 | + ADC_SoftwareStartConvCmd(adc, ENABLE); |
| 163 | + |
| 164 | +#if defined(SOC_SERIES_MM32F526) |
| 165 | + while (ADC_GetFlagStatus(adc, ADC_FLAG_EOC) == 0) |
| 166 | + { |
| 167 | + } |
| 168 | + ADC_ClearFlag(adc, ADC_FLAG_EOC); |
| 169 | + *value = ADC_GetChannelConvertedValue(adc, channel); |
| 170 | +#elif defined(SOC_SERIES_MM32F327) |
| 171 | + while (ADC_GetFlagStatus(adc, ADC_IT_EOC) == 0) |
| 172 | + { |
| 173 | + } |
| 174 | + ADC_ClearFlag(adc, ADC_IT_EOC); |
| 175 | + *value = ADC_GetConversionValue(adc); |
| 176 | +#endif |
| 177 | + |
| 178 | + return RT_EOK; |
| 179 | +} |
| 180 | + |
| 181 | +static rt_uint8_t mm32_adc_get_resolution(struct rt_adc_device *device) |
| 182 | +{ |
| 183 | + ADC_TypeDef *adc; |
| 184 | + rt_uint32_t resolution; |
| 185 | + |
| 186 | + RT_ASSERT(device != RT_NULL); |
| 187 | + adc = device->parent.user_data; |
| 188 | + |
| 189 | +#if defined(SOC_SERIES_MM32F526) |
| 190 | + resolution = adc->ADCFG & 0x00000380; |
| 191 | +#else |
| 192 | + resolution = adc->CFGR & 0x00000380; |
| 193 | +#endif |
| 194 | + |
| 195 | + switch (resolution) |
| 196 | + { |
| 197 | + case ADC_Resolution_12b: |
| 198 | + return 12; |
| 199 | + case ADC_Resolution_11b: |
| 200 | + return 11; |
| 201 | + case ADC_Resolution_10b: |
| 202 | + return 10; |
| 203 | + case ADC_Resolution_9b: |
| 204 | + return 9; |
| 205 | + case ADC_Resolution_8b: |
| 206 | + return 8; |
| 207 | + default: |
| 208 | + return 12; |
| 209 | + } |
| 210 | +} |
| 211 | + |
| 212 | +static rt_int16_t mm32_adc_get_vref(struct rt_adc_device *device) |
| 213 | +{ |
| 214 | + if (device == RT_NULL) |
| 215 | + { |
| 216 | + return -RT_ERROR; |
| 217 | + } |
| 218 | + |
| 219 | + return 3300; |
| 220 | +} |
| 221 | + |
| 222 | +static const struct rt_adc_ops mm32_adc_ops = |
| 223 | +{ |
| 224 | + .enabled = mm32_adc_enabled, |
| 225 | + .convert = mm32_adc_get_value, |
| 226 | + .get_resolution = mm32_adc_get_resolution, |
| 227 | + .get_vref = mm32_adc_get_vref, |
| 228 | +}; |
| 229 | + |
| 230 | +int rt_hw_adc_init(void) |
| 231 | +{ |
| 232 | + rt_size_t i; |
| 233 | + |
| 234 | + for (i = 0; i < sizeof(adc_obj) / sizeof(adc_obj[0]); i++) |
| 235 | + { |
| 236 | + if (rt_hw_adc_register(&adc_obj[i].device, adc_obj[i].name, &mm32_adc_ops, adc_obj[i].instance) != RT_EOK) |
| 237 | + { |
| 238 | + LOG_E("%s register failed", adc_obj[i].name); |
| 239 | + return -RT_ERROR; |
| 240 | + } |
| 241 | + } |
| 242 | + |
| 243 | + return RT_EOK; |
| 244 | +} |
| 245 | +INIT_BOARD_EXPORT(rt_hw_adc_init); |
| 246 | + |
| 247 | +#endif /* BSP_USING_ADC */ |
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