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boards/stm32f429i-disc1: fix fmc_sdram_bank_conf_t initializer order
C++20 requires designated initializers to follow struct declaration order, GCC rejects out-of-order designators as a hard error. This was latent in C builds but visibles when board headers are compiled as C++ (e.g. via pkg/radiolib), causing a Murdock CI failure. Reorder the initializer fields to match the struct declaration order. Signed-off-by: Baptiste Le Duc <baptiste.le-duc@vates.tech>
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Lines changed: 3 additions & 3 deletions

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boards/stm32f429i-disc1/include/periph_conf.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -207,12 +207,12 @@ static const fmc_bank_conf_t fmc_bank_config[] = {
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.col_bits = 8, /* A8..A0 used for column address */
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.cas_latency = 3, /* CAS latency is 3 clock cycles */
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.read_delay = 0, /* No read delay after CAS */
210+
.four_banks = true, /* SDRAM has four internal banks */
211+
.write_protect = false, /* No write protection */
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.burst_read = false, /* Burst read mode disabled */
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.burst_write = false, /* Burst write mode disabled */
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.burst_len = FMC_BURST_LENGTH_1, /* Burst length is 1 if enabled */
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.burst_interleaved = false, /* Burst mode interleaved */
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.write_protect = false, /* No write protection */
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.four_banks = true, /* SDRAM has four internal banks */
215+
.burst_len = FMC_BURST_LENGTH_1, /* Burst length is 1 if enabled */
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.timing = { /* SDRAM Timing parameters */
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.row_to_col_delay = 2, /* Row to column delay (2 clock cycles) */
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.row_precharge = 2, /* Row precharge delay (2 clock cycles) */

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