A few constraint files were renamed to maintain names coherency

Author: rodrigomelo9

examples/helpers/ise.sh

@@ -7,12 +7,12 @@ HDIR=../../pyfpga/helpers
 python3 $HDIR/hdl2bit.py -t ise -o results/ise-vlog -p xc6slx16-3-csg32 \
     -i ../sources/vlog/include1 -i ../sources/vlog/include2 \
     -f ../sources/vlog/blink.v -f ../sources/vlog/top.v \
-    -f ../sources/cons/nexys3/clk.xcf -f ../sources/cons/nexys3/clk.ucf -f ../sources/cons/nexys3/led.ucf \
+    -f ../sources/cons/nexys3/timing.xcf -f ../sources/cons/nexys3/clk.ucf -f ../sources/cons/nexys3/led.ucf \
     --define DEFINE1 1 --define DEFINE2 1 --param FREQ 125000000 --param SECS 1 Top
 
 python3 $HDIR/hdl2bit.py -t ise -o results/ise-vhdl -p xc6slx16-3-csg32 --project example \
     -f ../sources/vhdl/blink.vhdl,blink_lib -f ../sources/vhdl/blink_pkg.vhdl,blink_lib -f ../sources/vhdl/top.vhdl \
-    -f ../sources/cons/nexys3/clk.xcf -f ../sources/cons/nexys3/clk.ucf -f ../sources/cons/nexys3/led.ucf \
+    -f ../sources/cons/nexys3/timing.xcf -f ../sources/cons/nexys3/clk.ucf -f ../sources/cons/nexys3/led.ucf \
     --param FREQ 125000000 --param SECS 1 --last cfg Top
 
 python3 $HDIR/prj2bit.py results/ise-vhdl/example.xise

examples/helpers/libero.sh

@@ -7,12 +7,12 @@ HDIR=../../pyfpga/helpers
 python3 $HDIR/hdl2bit.py -t libero -o results/libero-vlog -p m2s010-1-tq144 \
     -i ../sources/vlog/include1 -i ../sources/vlog/include2 \
     -f ../sources/vlog/blink.v -f ../sources/vlog/top.v \
-    -f ../sources/cons/maker/clk.sdc -f ../sources/cons/maker/clk.pdc -f ../sources/cons/maker/led.pdc \
+    -f ../sources/cons/maker/timing.sdc -f ../sources/cons/maker/clk.pdc -f ../sources/cons/maker/led.pdc \
     --define DEFINE1 1 --define DEFINE2 1 --param FREQ 125000000 --param SECS 1 Top
 
 python3 $HDIR/hdl2bit.py -t libero -o results/libero-vhdl -p m2s010-1-tq144 --project example \
     -f ../sources/vhdl/blink.vhdl,blink_lib -f ../sources/vhdl/blink_pkg.vhdl,blink_lib -f ../sources/vhdl/top.vhdl \
-    -f ../sources/cons/maker/clk.sdc -f ../sources/cons/maker/clk.pdc -f ../sources/cons/maker/led.pdc \
+    -f ../sources/cons/maker/timing.sdc -f ../sources/cons/maker/clk.pdc -f ../sources/cons/maker/led.pdc \
     --param FREQ 125000000 --param SECS 1 --last cfg Top
 
 python3 $HDIR/prj2bit.py results/libero-vhdl/libero/example.prjx

examples/helpers/quartus.sh

@@ -7,12 +7,12 @@ HDIR=../../pyfpga/helpers
 python3 $HDIR/hdl2bit.py -t quartus -o results/quartus-vlog -p 5CSEBA6U23I7 \
     -i ../sources/vlog/include1 -i ../sources/vlog/include2 \
     -f ../sources/vlog/blink.v -f ../sources/vlog/top.v \
-    -f ../sources/cons/de10nano/clk.sdc -f ../sources/cons/de10nano/clk.tcl -f ../sources/cons/de10nano/led.tcl \
+    -f ../sources/cons/de10nano/timing.sdc -f ../sources/cons/de10nano/clk.tcl -f ../sources/cons/de10nano/led.tcl \
     --define DEFINE1 1 --define DEFINE2 1 --param FREQ 125000000 --param SECS 1 Top
 
 python3 $HDIR/hdl2bit.py -t quartus -o results/quartus-vhdl -p 5CSEBA6U23I7 --project example \
     -f ../sources/vhdl/blink.vhdl,blink_lib -f ../sources/vhdl/blink_pkg.vhdl,blink_lib -f ../sources/vhdl/top.vhdl \
-    -f ../sources/cons/de10nano/clk.sdc -f ../sources/cons/de10nano/clk.tcl -f ../sources/cons/de10nano/led.tcl \
+    -f ../sources/cons/de10nano/timing.sdc -f ../sources/cons/de10nano/clk.tcl -f ../sources/cons/de10nano/led.tcl \
     --param FREQ 125000000 --param SECS 1 --last cfg Top
 
 python3 $HDIR/prj2bit.py results/quartus-vhdl/example.qpf

examples/hooks/diamond.py

@@ -33,9 +33,8 @@
 prj.add_param('FREQ', '50000000')
 prj.add_param('SECS', '1')
 
-prj.add_cons('../sources/cons/brevia2/clk.lpf', 'syn')
-prj.add_cons('../sources/cons/brevia2/clk.lpf', 'par')
-prj.add_cons('../sources/cons/brevia2/io.lpf', 'par')
+prj.add_cons('../sources/cons/brevia2/clk.lpf')
+prj.add_cons('../sources/cons/brevia2/led.lpf')
 
 prj.add_include('../sources/vlog/include1')
 prj.add_include('../sources/vlog/include2')

examples/projects/diamond.py

@@ -22,9 +22,8 @@
 if args.board == 'brevia2':
     prj.set_part('LFXP2-5E-5TN144C')
     prj.add_param('FREQ', '50000000')
-    prj.add_cons('../sources/cons/brevia2/clk.lpf', 'syn')
-    prj.add_cons('../sources/cons/brevia2/clk.lpf', 'par')
-    prj.add_cons('../sources/cons/brevia2/io.lpf', 'par')
+    prj.add_cons('../sources/cons/brevia2/clk.lpf')
+    prj.add_cons('../sources/cons/brevia2/led.lpf')
 prj.add_param('SECS', '1')
 
 if args.source == 'vhdl':

examples/projects/ise.py

@@ -22,13 +22,13 @@
 if args.board == 's6micro':
     prj.set_part('xc6slx9-2-csg324')
     prj.add_param('FREQ', '125000000')
-    prj.add_cons('../sources/cons/s6micro/clk.xcf')
+    prj.add_cons('../sources/cons/s6micro/timing.xcf')
     prj.add_cons('../sources/cons/s6micro/clk.ucf')
     prj.add_cons('../sources/cons/s6micro/led.ucf')
 if args.board == 'nexys3':
     prj.set_part('xc6slx16-3-csg32')
     prj.add_param('FREQ', '100000000')
-    prj.add_cons('../sources/cons/nexys3/clk.xcf')
+    prj.add_cons('../sources/cons/nexys3/timing.xcf')
     prj.add_cons('../sources/cons/nexys3/clk.ucf')
     prj.add_cons('../sources/cons/nexys3/led.ucf')
 prj.add_param('SECS', '1')

examples/projects/libero.py

@@ -21,7 +21,7 @@
 if args.board == 'maker':
     prj.set_part('m2s010-1-tq144')
     prj.add_param('FREQ', '125000000')
-    prj.add_cons('../sources/cons/maker/clk.sdc')
+    prj.add_cons('../sources/cons/maker/timing.sdc')
     prj.add_cons('../sources/cons/maker/clk.pdc')
     prj.add_cons('../sources/cons/maker/led.pdc')
 prj.add_param('SECS', '1')

examples/projects/quartus.py

@@ -22,7 +22,7 @@
 if args.board == 'de10nano':
     prj.set_part('5CSEBA6U23I7')
     prj.add_param('FREQ', '125000000')
-    prj.add_cons('../sources/cons/de10nano/clk.sdc')
+    prj.add_cons('../sources/cons/de10nano/timing.sdc')
     prj.add_cons('../sources/cons/de10nano/clk.tcl')
     prj.add_cons('../sources/cons/de10nano/led.tcl')
 prj.add_param('SECS', '1')