add interrupts and timers, passes blargg 2

Ptival · Ptival · commit ebaa17c8fe0b · 2024-09-02T02:00:47.000-07:00
diff --git a/.gitignore b/.gitignore
@@ -1,3 +1,6 @@
 *.bin
 *.pdf
+.vscode
+log
 /target
+/roms
diff --git a/src/cpu.rs b/src/cpu.rs
@@ -1,5 +1,11 @@
+pub mod interrupts;
+pub mod timers;
+
 use std::num::Wrapping;
 
+use interrupts::Interrupts;
+use timers::Timers;
+
 use crate::{
     instructions::{decode::decode_instruction_at_address, type_def::Immediate16},
     machine::Machine,
@@ -9,19 +15,32 @@ use crate::{
 
 #[derive(Clone, Debug, Hash)]
 pub struct CPU {
+    pub low_power_mode: bool,
+    pub interrupts: Interrupts,
     pub memory: Memory,
     pub registers: Registers,
+    pub timers: Timers,
 }
 
 impl CPU {
     pub fn new() -> Self {
         CPU {
+            low_power_mode: false,
+            interrupts: Interrupts::new(),
             memory: Memory::new(),
             registers: Registers::new(),
+            timers: Timers::new(),
         }
     }
 
     pub fn execute_one_instruction(machine: &mut Machine) -> (u8, u8) {
+        if machine.cpu.low_power_mode {
+            if Interrupts::is_interrupt_pending(machine) {
+                machine.cpu.low_power_mode = false;
+            }
+            // Forces the other components to move forward
+            return (4, 1);
+        }
         let next_instruction = decode_instruction_at_address(machine, machine.cpu.registers.pc);
         // This will be the default PC, unless instruction semantics overwrite it
         machine.cpu.registers.pc =
diff --git a/src/cpu/interrupts.rs b/src/cpu/interrupts.rs
@@ -0,0 +1,93 @@
+use std::num::Wrapping;
+
+use crate::{instructions::type_def::Immediate16, machine::Machine};
+
+use super::CPU;
+
+pub const VBLANK_INTERRUPT_BIT: u8 = 0;
+const VBLANK_INTERRUPT_ADDRESS: u16 = 0x40;
+pub const STAT_INTERRUPT_BIT: u8 = 1;
+const STAT_INTERRUPT_ADDRESS: u16 = 0x48;
+pub const TIMER_INTERRUPT_BIT: u8 = 2;
+const TIMER_INTERRUPT_ADDRESS: u16 = 0x50;
+pub const SERIAL_INTERRUPT_BIT: u8 = 3;
+const SERIAL_INTERRUPT_ADDRESS: u16 = 0x58;
+pub const JOYPAD_INTERRUPT_BIT: u8 = 4;
+const JOYPAD_INTERRUPT_ADDRESS: u16 = 0x60;
+
+#[derive(Clone, Debug, Hash)]
+pub struct Interrupts {
+    pub interrupt_master_enable: bool,
+    pub interrupt_master_enable_delayed: bool,
+    pub interrupt_enable: Wrapping<u8>,
+    pub interrupt_flag: Wrapping<u8>,
+}
+
+// Returns the bit index of the interrupt to handle (0 = VBlank... 4 = Joypad)
+fn should_handle_interrupt(machine: &mut Machine) -> Option<u8> {
+    if !machine.cpu.interrupts.interrupt_master_enable {
+        return None;
+    }
+    let masked_ie = machine.cpu.interrupts.interrupt_enable.0 & 0x1F;
+    let masked_if = machine.cpu.interrupts.interrupt_flag.0 & 0x1F;
+    let conjoined = masked_ie & masked_if;
+    // 0 has most priority, 4 has least
+    for i in 0..5 {
+        let mask = 1 << i;
+        if (conjoined & mask) == mask {
+            return Some(i);
+        }
+    }
+    None
+}
+
+fn interrupt_handler_offset(interrupt_bit: u8) -> Wrapping<u16> {
+    Wrapping(match interrupt_bit {
+        VBLANK_INTERRUPT_BIT => VBLANK_INTERRUPT_ADDRESS,
+        STAT_INTERRUPT_BIT => STAT_INTERRUPT_ADDRESS,
+        TIMER_INTERRUPT_BIT => TIMER_INTERRUPT_ADDRESS,
+        SERIAL_INTERRUPT_BIT => SERIAL_INTERRUPT_ADDRESS,
+        JOYPAD_INTERRUPT_BIT => JOYPAD_INTERRUPT_ADDRESS,
+        _ => unreachable!(),
+    })
+}
+
+impl Interrupts {
+    pub fn new() -> Self {
+        Interrupts {
+            interrupt_master_enable: false,
+            interrupt_master_enable_delayed: false,
+            interrupt_enable: Wrapping(0),
+            interrupt_flag: Wrapping(0),
+        }
+    }
+
+    pub fn handle_interrupts(machine: &mut Machine) -> (u8, u8) {
+        if let Some(interrupt) = should_handle_interrupt(machine) {
+            println!("Handling interrupt {}", interrupt);
+            machine.cpu.interrupts.interrupt_flag =
+                machine.cpu.interrupts.interrupt_flag & Wrapping(!(1 << interrupt));
+            machine.cpu.interrupts.interrupt_master_enable = false;
+            // Here the CPU:
+            // - NOPs twice (2 M-cycles)
+            // - PUSHes PC (2 M-cycles)
+            // - sets PC to the handle (1 M-cycle)
+            // Currently simulating this whole thing at once, but might need granularity
+            CPU::push_imm16(machine, Immediate16::from_u16(machine.cpu.registers.pc));
+            machine.cpu.registers.pc = interrupt_handler_offset(interrupt);
+            (20, 5)
+        } else {
+            (0, 0)
+        }
+    }
+
+    pub fn is_interrupt_pending(machine: &Machine) -> bool {
+        let masked_ie = machine.cpu.interrupts.interrupt_enable.0 & 0x1F;
+        let masked_if = machine.cpu.interrupts.interrupt_flag.0 & 0x1F;
+        (masked_ie & masked_if) != 0
+    }
+
+    pub fn request_interrupt(&mut self, interrupt_bit: u8) {
+        self.interrupt_flag |= 1 << interrupt_bit;
+    }
+}
diff --git a/src/cpu/timers.rs b/src/cpu/timers.rs
@@ -0,0 +1,104 @@
+use std::num::Wrapping;
+
+use crate::machine::Machine;
+
+use super::interrupts::TIMER_INTERRUPT_BIT;
+
+const DIVIDE_REGISTER_ADDRESS: u16 = 0xFF04;
+const TIMER_COUNTER_ADDRESS: u16 = 0xFF05;
+const TIMER_MODULO_ADDRESS: u16 = 0xFF06;
+const TIMER_CONTROL_ADDRESS: u16 = 0xFF07;
+
+#[derive(Clone, Debug, Hash)]
+pub struct Timers {
+    pub divide_register: Wrapping<u8>,
+    divide_register_dots: u16,
+    // When we reset this, we must account for the fact that the reset would happen at the end of
+    // the resetting instruction, rather than the beginning.  So we mark this to know to reset it
+    // later.
+    divide_register_to_be_reset: bool,
+    pub timer_counter: Wrapping<u8>,
+    timer_counter_dots: u16,
+    pub timer_modulo: Wrapping<u8>,
+    pub timer_control: Wrapping<u8>,
+}
+
+fn get_timer_counter_threshold(machine: &mut Machine) -> u16 {
+    match machine.cpu.timers.timer_control.0 & 0x3 {
+        0b00 => 1024,
+        0b01 => 16,
+        0b10 => 64,
+        0b11 => 256,
+        _ => unreachable!(),
+    }
+}
+
+impl Timers {
+    pub fn new() -> Self {
+        Timers {
+            divide_register: Wrapping(0),
+            divide_register_to_be_reset: false,
+            divide_register_dots: 0,
+            timer_counter: Wrapping(0),
+            timer_counter_dots: 0,
+            timer_modulo: Wrapping(0),
+            timer_control: Wrapping(0),
+        }
+    }
+
+    fn step_one_dot(machine: &mut Machine) {
+        machine.cpu.timers.divide_register_dots += 1;
+        if machine.cpu.timers.divide_register_dots == 256 {
+            machine.cpu.timers.divide_register_dots = 0;
+            machine.cpu.timers.divide_register += 1;
+        }
+
+        if (machine.cpu.timers.timer_control.0 & 0b100) != 0 {
+            machine.cpu.timers.timer_counter_dots += 1;
+            if machine.cpu.timers.timer_counter_dots == get_timer_counter_threshold(machine) {
+                machine.cpu.timers.timer_counter_dots = 0;
+                machine.cpu.timers.timer_counter += 1;
+                if machine.cpu.timers.timer_counter.0 == 0 {
+                    machine.cpu.timers.timer_counter = machine.cpu.timers.timer_modulo;
+                    machine.request_interrupt(TIMER_INTERRUPT_BIT);
+                }
+            }
+        }
+    }
+
+    pub fn step_dots(machine: &mut Machine, dots: u8) {
+        for _ in 0..dots {
+            Self::step_one_dot(machine);
+        }
+        if machine.cpu.timers.divide_register_to_be_reset {
+            machine.cpu.timers.divide_register_to_be_reset = false;
+            machine.cpu.timers.divide_register = Wrapping(0);
+        }
+    }
+
+    pub fn read_u8(&self, address: Wrapping<u16>) -> Wrapping<u8> {
+        match address.0 {
+            DIVIDE_REGISTER_ADDRESS => self.divide_register,
+            TIMER_COUNTER_ADDRESS => self.timer_counter,
+            TIMER_MODULO_ADDRESS => self.timer_modulo,
+            TIMER_CONTROL_ADDRESS => self.timer_control,
+            _ => unreachable!(),
+        }
+    }
+
+    pub fn write_u8(&mut self, address: Wrapping<u16>, value: Wrapping<u8>) {
+        match address.0 {
+            DIVIDE_REGISTER_ADDRESS => {
+                // Writing any value to this register resets it.  However, if we were to reset it
+                // here for a 4 t-cycle instruction, it would have started counting 4 by the time
+                // where it should actually be reset.  So instead we mark it to be reset after
+                // simulating the current instruction's t-cycles.
+                self.divide_register_to_be_reset = true;
+            }
+            TIMER_COUNTER_ADDRESS => self.timer_counter = value,
+            TIMER_MODULO_ADDRESS => self.timer_modulo = value,
+            TIMER_CONTROL_ADDRESS => self.timer_control = value,
+            _ => unreachable!(),
+        }
+    }
+}
diff --git a/src/instructions/decode.rs b/src/instructions/decode.rs
@@ -178,7 +178,7 @@ pub fn decode_instruction_at_address(
         0x73 => Instruction::LD_mr16_r8(R16::HL, R8::E),
         0x74 => Instruction::LD_mr16_r8(R16::HL, R8::H),
         0x75 => Instruction::LD_mr16_r8(R16::HL, R8::L),
-        0x76 => todo!(),
+        0x76 => Instruction::HALT,
         0x77 => Instruction::LD_mr16_r8(R16::HL, R8::A),
         0x78 => Instruction::LD_r8_r8(R8::A, R8::B),
         0x79 => Instruction::LD_r8_r8(R8::A, R8::C),
diff --git a/src/instructions/display.rs b/src/instructions/display.rs
@@ -33,6 +33,7 @@ impl DecodedInstruction {
             Instruction::DEC_r8(r8) => format!("DEC {}", r8),
             Instruction::DI => String::from("DI"),
             Instruction::EI => String::from("EI"),
+            Instruction::HALT => String::from("HALT"),
             Instruction::Illegal(opcode) => format!("ILLEGAL 0x{:02X}", opcode),
             Instruction::INC_mHL => String::from("INC [HL]"),
             Instruction::INC_r16(r16) => format!("INC {}", r16),
diff --git a/src/instructions/semantics.rs b/src/instructions/semantics.rs
@@ -1,7 +1,7 @@
 use std::num::Wrapping;
 
 use crate::{
-    cpu::CPU,
+    cpu::{interrupts::Interrupts, CPU},
     machine::Machine,
     registers::{Flag, R16, R8},
 };
@@ -114,6 +114,12 @@ fn call(machine: &mut Machine, address: Wrapping<u16>) {
 
 impl Instruction {
     pub fn execute(self: &Instruction, machine: &mut Machine) -> (u8, u8) {
+        // EI effects are delayed by one instruction, we resolve it here
+        if machine.cpu.interrupts.interrupt_master_enable_delayed {
+            machine.cpu.interrupts.interrupt_master_enable_delayed = false;
+            machine.cpu.interrupts.interrupt_master_enable = true;
+        }
+
         match self {
             Instruction::ADC_A_r8(r8) => {
                 let a = machine.cpu.registers.read_a();
@@ -280,13 +286,26 @@ impl Instruction {
             }
 
             Instruction::DI => {
-                machine.cpu.registers.ime = false;
+                machine.cpu.interrupts.interrupt_master_enable = false;
                 (4, 1)
             }
 
+            // NOTE: This sets up IME in one instruction
             Instruction::EI => {
-                // FIXME: This should apparently be delayed until the next instruction has finished.
-                machine.cpu.registers.ime = true;
+                machine.cpu.interrupts.interrupt_master_enable_delayed = true;
+                (4, 1)
+            }
+
+            Instruction::HALT => {
+                if machine.cpu.interrupts.interrupt_master_enable {
+                    machine.cpu.low_power_mode = true;
+                } else {
+                    if Interrupts::is_interrupt_pending(machine) {
+                        panic!("Need to emulate HALT bug");
+                    } else {
+                        machine.cpu.low_power_mode = true;
+                    }
+                }
                 (4, 1)
             }
 
@@ -562,8 +581,7 @@ impl Instruction {
             }
 
             Instruction::RETI => {
-                // TODO: Handle IME delay
-                machine.cpu.registers.ime = true;
+                machine.cpu.interrupts.interrupt_master_enable = true;
                 CPU::pop_r16(machine, &R16::PC);
                 (16, 4)
             }
diff --git a/src/instructions/type_def.rs b/src/instructions/type_def.rs
@@ -58,6 +58,7 @@ pub enum Instruction {
     DEC_r8(R8),
     DI,
     EI,
+    HALT,
     INC_mHL,
     INC_r16(R16),
     INC_r8(R8),
diff --git a/src/machine.rs b/src/machine.rs
diff --git a/src/main.rs b/src/main.rs
diff --git a/src/ppu.rs b/src/ppu.rs
diff --git a/src/registers.rs b/src/registers.rs

-Original file line number
+Diff line change
@@ @@ -1,3 +1,6 @@ @@
 *.bin
 *.pdf
 +.vscode
 +log
 /target
 +/roms