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ashishsinghajgarver
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fix(smmuv3): reset strtab currently used
reset the stream tables used by smmu at the time of smmu being put in global bypass. Signed-off-by: Ashish Singhal <[email protected]> Reviewed-by: Abhishek Mainkar <[email protected]> Reviewed-by: Jake Garver <[email protected]> Tested-by: Jake Garver <[email protected]>
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Silicon/NVIDIA/Drivers/SmmuV3Dxe/SmmuV3Dxe.c

Lines changed: 16 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -2388,11 +2388,6 @@ OnReadyToBoot (
23882388
)
23892389
{
23902390
SMMU_V3_CONTROLLER_PRIVATE_DATA *Private;
2391-
UINT32 GbpSetting;
2392-
2393-
/*UINT32 SteCount;
2394-
UINT32 Index;
2395-
UINT64 *SteS2TtbAddr;*/
23962391

23972392
gBS->CloseEvent (Event);
23982393

@@ -2404,18 +2399,20 @@ OnReadyToBoot (
24042399

24052400
Private->ReadyToBootEvent = NULL;
24062401

2407-
if (Private->CmdQueue.QBase != 0) {
2408-
FreeAlignedPages ((VOID *)Private->CmdQueue.QBase, EFI_SIZE_TO_PAGES ((1 << Private->Features.CmdqEntriesLog2) * SMMU_V3_CMD_SIZE));
2409-
}
2402+
// Reset the controller into global bypass mode
2403+
ResetSmmuV3Controller (Private);
24102404

2411-
if (Private->EvtQueue.QBase != 0) {
2412-
FreeAlignedPages ((VOID *)Private->EvtQueue.QBase, EFI_SIZE_TO_PAGES ((1 << Private->Features.EvtqEntriesLog2) * SMMU_V3_EVT_RECORD_SIZE));
2413-
}
2405+
// Clear Stream Tables
2406+
MmioWrite64 (Private->BaseAddress + SMMU_V3_STRTAB_BASE_OFFSET, 0);
2407+
MmioWrite32 (Private->BaseAddress + SMMU_V3_STRTAB_BASE_CFG_OFFSET, 0);
24142408

24152409
if (Private->SteBase != 0) {
24162410
FreeAlignedPages ((VOID *)Private->SteBase, EFI_SIZE_TO_PAGES ((1 << Private->Features.StreamNBits) * SMMU_V3_STRTAB_ENTRY_SIZE));
24172411
}
24182412

2413+
// Invalidate cached configurations and TLBs
2414+
InvalidateCachedCfgsTlbs (Private);
2415+
24192416
// Disable Command Queue
24202417
MmioBitFieldWrite32 (
24212418
Private->BaseAddress + SMMU_V3_CR0_OFFSET,
@@ -2431,6 +2428,10 @@ OnReadyToBoot (
24312428
return;
24322429
}
24332430

2431+
if (Private->CmdQueue.QBase != 0) {
2432+
FreeAlignedPages ((VOID *)Private->CmdQueue.QBase, EFI_SIZE_TO_PAGES ((1 << Private->Features.CmdqEntriesLog2) * SMMU_V3_CMD_SIZE));
2433+
}
2434+
24342435
// Disable Event Queue
24352436
MmioBitFieldWrite32 (
24362437
Private->BaseAddress + SMMU_V3_CR0_OFFSET,
@@ -2446,6 +2447,10 @@ OnReadyToBoot (
24462447
return;
24472448
}
24482449

2450+
if (Private->EvtQueue.QBase != 0) {
2451+
FreeAlignedPages ((VOID *)Private->EvtQueue.QBase, EFI_SIZE_TO_PAGES ((1 << Private->Features.EvtqEntriesLog2) * SMMU_V3_EVT_RECORD_SIZE));
2452+
}
2453+
24492454
// Clear page tables
24502455

24512456
/*if (Private->SteS2TtbBaseAddresses != 0) {
@@ -2460,37 +2465,6 @@ OnReadyToBoot (
24602465
24612466
//FreePages ((VOID *)Private->SteS2TtbBaseAddresses, EFI_SIZE_TO_PAGES ((1 << Private->Features.StreamNBits) * sizeof (EFI_PHYSICAL_ADDRESS)));
24622467
}*/
2463-
2464-
// Set the controller in global bypass mode
2465-
GbpSetting = BIT_FIELD_SET (1U, SMMU_V3_GBPA_UPDATE_MASK, SMMU_V3_GBPA_UPDATE_SHIFT);
2466-
GbpSetting = GbpSetting | BIT_FIELD_SET (0, SMMU_V3_GBPA_ABORT_MASK, SMMU_V3_GBPA_ABORT_SHIFT);
2467-
GbpSetting = GbpSetting | BIT_FIELD_SET (0, SMMU_V3_GBPA_INSTCFG_MASK, SMMU_V3_GBPA_INSTCFG_SHIFT);
2468-
GbpSetting = GbpSetting | BIT_FIELD_SET (0, SMMU_V3_GBPA_PRIVCFG_MASK, SMMU_V3_GBPA_PRIVCFG_SHIFT);
2469-
GbpSetting = GbpSetting | BIT_FIELD_SET (1, SMMU_V3_GBPA_SHCFG_MASK, SMMU_V3_GBPA_SHCFG_SHIFT);
2470-
GbpSetting = GbpSetting | BIT_FIELD_SET (0, SMMU_V3_GBPA_ALLOCFG_MASK, SMMU_V3_GBPA_ALLOCFG_SHIFT);
2471-
GbpSetting = GbpSetting | BIT_FIELD_SET (0, SMMU_V3_GBPA_MTCFG_MASK, SMMU_V3_GBPA_MTCFG_SHIFT);
2472-
MmioWrite32 (Private->BaseAddress + SMMU_V3_GBPA_OFFSET, GbpSetting);
2473-
2474-
// Wait for the controller to enter global bypass mode
2475-
gBS->Stall (10000);
2476-
if (((MmioRead32 (Private->BaseAddress + SMMU_V3_GBPA_OFFSET) >> SMMU_V3_GBPA_UPDATE_SHIFT) & SMMU_V3_GBPA_UPDATE_MASK) == 1) {
2477-
DEBUG ((DEBUG_ERROR, "%a: Unable to put SMMU in global bypass mode 0x%lx\n", __FUNCTION__, Private->BaseAddress));
2478-
return;
2479-
}
2480-
2481-
MmioBitFieldWrite32 (
2482-
Private->BaseAddress + SMMU_V3_CR0_OFFSET,
2483-
SMMU_V3_CR0_SMMUEN_BIT,
2484-
SMMU_V3_CR0_SMMUEN_BIT,
2485-
SMMU_V3_DISABLE
2486-
);
2487-
2488-
// Wait for the controller to disable SMMU operation
2489-
gBS->Stall (10000);
2490-
if (((MmioRead32 (Private->BaseAddress + SMMU_V3_CR0ACK_OFFSET) >> SMMU_V3_CR0ACK_SMMUEN_SHIFT) & SMMU_V3_CR0ACK_SMMUEN_MASK) != SMMU_V3_DISABLE) {
2491-
DEBUG ((DEBUG_ERROR, "%a: Unable disable SMMU 0x%lx\n", __FUNCTION__, Private->BaseAddress));
2492-
return;
2493-
}
24942468
}
24952469

24962470
/**

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