diff --git a/css/zubpm.bob b/css/zubpm.bob index 4ddc380..f46f1f4 100644 --- a/css/zubpm.bob +++ b/css/zubpm.bob @@ -1,5 +1,5 @@ - + $(PRI):$(Sec)-BPM$(N)LN_LTB_bpm_Ctrl 1350 @@ -3321,6 +3321,56 @@ $(pv_value) + + Boolean Button_6 + $(PRI)-BI{BPM:$(N)}ADC:MMCM0DLY-SP + 838 + 12 + 183 + 29 + ADC0 MMCM DLYSTR + + + + + Trin On + + + + + + + + + + + 1 + + + Boolean Button_7 + $(PRI)-BI{BPM:$(N)}ADC:MMCM1DLY-SP + 1048 + 6 + 183 + 29 + ADC1 MMCM DLYSTR + + + + + Trin On + + + + + + + + + + + 1 + @@ -5785,6 +5835,42 @@ $(pv_value) 1.0E8 false + + Spinner_17 + $(PRI)-BI{BPM:$(N)}ADC:IDLY-SP + 147 + 499 + 79 + 25 + 0 + 3 + + + + + 1 + 1 + + + 1.0E8 + false + + + Label_85 + ADC idly + 54 + 493 + 107 + 36 + 1 + 1 + + + + + + + @@ -5925,16 +6011,53 @@ $(pv_value) - 37 - 29 + 36 + 30 1290 734 + 2 10 + + Spinner_18 + $(PRI)-BI{BPM:$(N)}ADC:IDLY-SP + 762 + 97 + 79 + 25 + 0 + 3 + + + + + 1 + 1 + + + 1.0E8 + false + + + Label_87 + ADC idly + 669 + 91 + 107 + 36 + 1 + 1 + + + + + + + diff --git a/ioc/st.cmd b/ioc/st.cmd index 0cea22f..681101c 100755 --- a/ioc/st.cmd +++ b/ioc/st.cmd @@ -1,7 +1,7 @@ -#!//home/diag/epics/pscdrv/bin/linux-x86_64/pscdemo -epicsEnvSet("TOP","/home/diag/epics/pscdrv") +#!//home/mead/epics/pscdrv/bin/linux-x86_64/pscdemo +epicsEnvSet("TOP","/home/mead/epics/pscdrv") epicsEnvSet("BPMDIR","$(TOP)") -epicsEnvSet("ZUBPM_DBDIR","/home/diag/fwk/zubpm/ioc") +epicsEnvSet("ZUBPM_DBDIR","/home/mead/rfbpm/fwk/zubpm/ioc") #epicsEnvSet("CNO","40") ## Cell Number @@ -54,8 +54,8 @@ var(PSCDebug, 5) #5 full debug #bpm1 Create the PSC createPSC("aie_tx_1", $(BPM1_IP), 7, 0) -createPSC("aie_wfm_rx_1", $(BPM1_IP), 20, 2) -createPSC("Rx1", $(BPM1_IP), 600, 2) +createPSC("aie_wfm_rx_1", $(BPM1_IP), 20, 1) +createPSC("Rx1", $(BPM1_IP), 600, 1) ########### iocInit diff --git a/ioc/zubpm.db b/ioc/zubpm.db index 5f0b2cd..85725a0 100644 --- a/ioc/zubpm.db +++ b/ioc/zubpm.db @@ -75,10 +75,35 @@ record(bo, "$(P){BPM:$(NO)}Rf:PtPwr-SP") { } #ADC IDLY Value -record(bo, "$(P){BPM:$(NO)}ADC:IDLY-SP") { +record(ao, "$(P){BPM:$(NO)}ADC:IDLY-SP") { field(DESC, "ADC IDLY Ctrl") - field(DTYP, "PSC Single U32") + field(DTYP, "PSC Single I32") field(OUT , "@aie_tx_$(NO) 1 12") + info(autosaveFields, "VAL") + field(FLNK, "$(P){BPM:$(NO)}GoRegSingleWrite") +} + + + + +#ADC FCO MMCM Delay Strobe +record(bo, "$(P){BPM:$(NO)}ADC:MMCM0DLY-SP") { + field(DESC, "MMCM0 FCO Delay Strobe") + field(DTYP, "PSC Single U32") + #field(DOL , "$(SYS=SR)-HLA{}AllBPMs-Rf:PtPwr-SP CP") + field(OUT , "@aie_tx_$(NO) 1 16") + field(ZNAM,"Off") + field(ONAM,"On") + info(autosaveFields, "VAL") + field(FLNK, "$(P){BPM:$(NO)}GoRegSingleWrite") +} + +#ADC FCO MMCM Delay Strobe +record(bo, "$(P){BPM:$(NO)}ADC:MMCM1DLY-SP") { + field(DESC, "MMCM1 FCO Delay Strobe") + field(DTYP, "PSC Single U32") + #field(DOL , "$(SYS=SR)-HLA{}AllBPMs-Rf:PtPwr-SP CP") + field(OUT , "@aie_tx_$(NO) 1 20") field(ZNAM,"Off") field(ONAM,"On") info(autosaveFields, "VAL") @@ -90,6 +115,7 @@ record(bo, "$(P){BPM:$(NO)}ADC:IDLY-SP") { + #Trigger source (Internal/External) record(bo, "$(P){BPM:$(NO)}Trig:TrigSrc-SP") { field(DESC, "Trigger source") diff --git a/src/hw/cstr/afepins.xdc b/src/hw/cstr/afepins.xdc index 6d1d277..614efb1 100644 --- a/src/hw/cstr/afepins.xdc +++ b/src/hw/cstr/afepins.xdc @@ -296,3 +296,4 @@ set_property DIFF_TERM_ADV TERM_100 [get_ports {adc_sdata_n[15]}] + diff --git a/src/hw/cstr/debug.xdc b/src/hw/cstr/debug.xdc index 0357761..1461861 100644 --- a/src/hw/cstr/debug.xdc +++ b/src/hw/cstr/debug.xdc @@ -2,96 +2,88 @@ create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] -set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0] set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property port_width 1 [get_debug_ports u_ila_0/clk] -connect_debug_port u_ila_0/clk [get_nets [list evr/evr_rcvd_clk]] +connect_debug_port u_ila_0/clk [get_nets [list system_i/zynq_ultra_ps_e_0/U0/pl_clk0]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -set_property port_width 16 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {evr/gth_rx_userdata[0]} {evr/gth_rx_userdata[1]} {evr/gth_rx_userdata[2]} {evr/gth_rx_userdata[3]} {evr/gth_rx_userdata[4]} {evr/gth_rx_userdata[5]} {evr/gth_rx_userdata[6]} {evr/gth_rx_userdata[7]} {evr/gth_rx_userdata[8]} {evr/gth_rx_userdata[9]} {evr/gth_rx_userdata[10]} {evr/gth_rx_userdata[11]} {evr/gth_rx_userdata[12]} {evr/gth_rx_userdata[13]} {evr/gth_rx_userdata[14]} {evr/gth_rx_userdata[15]}]] +set_property port_width 5 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {adc_inst/adc_spi/bcnt[0]} {adc_inst/adc_spi/bcnt[1]} {adc_inst/adc_spi/bcnt[2]} {adc_inst/adc_spi/bcnt[3]} {adc_inst/adc_spi/bcnt[4]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -set_property port_width 8 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {evr/datastream[0]} {evr/datastream[1]} {evr/datastream[2]} {evr/datastream[3]} {evr/datastream[4]} {evr/datastream[5]} {evr/datastream[6]} {evr/datastream[7]}]] +set_property port_width 2 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {adc_inst/adc_spi/csb[0]} {adc_inst/adc_spi/csb[1]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -set_property port_width 8 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {evr/eventstream[0]} {evr/eventstream[1]} {evr/eventstream[2]} {evr/eventstream[3]} {evr/eventstream[4]} {evr/eventstream[5]} {evr/eventstream[6]} {evr/eventstream[7]}]] +set_property port_width 16 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {adc_inst/adc_spi/spi_wdata[0]} {adc_inst/adc_spi/spi_wdata[1]} {adc_inst/adc_spi/spi_wdata[2]} {adc_inst/adc_spi/spi_wdata[3]} {adc_inst/adc_spi/spi_wdata[4]} {adc_inst/adc_spi/spi_wdata[5]} {adc_inst/adc_spi/spi_wdata[6]} {adc_inst/adc_spi/spi_wdata[7]} {adc_inst/adc_spi/spi_wdata[8]} {adc_inst/adc_spi/spi_wdata[9]} {adc_inst/adc_spi/spi_wdata[10]} {adc_inst/adc_spi/spi_wdata[11]} {adc_inst/adc_spi/spi_wdata[12]} {adc_inst/adc_spi/spi_wdata[13]} {adc_inst/adc_spi/spi_wdata[14]} {adc_inst/adc_spi/spi_wdata[15]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -set_property port_width 8 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {evr/gth_rxctrl2[0]} {evr/gth_rxctrl2[1]} {evr/gth_rxctrl2[2]} {evr/gth_rxctrl2[3]} {evr/gth_rxctrl2[4]} {evr/gth_rxctrl2[5]} {evr/gth_rxctrl2[6]} {evr/gth_rxctrl2[7]}]] +set_property port_width 2 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {adc_inst/adc_spi/sdo[0]} {adc_inst/adc_spi/sdo[1]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -set_property port_width 64 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {evr/timestamp[0]} {evr/timestamp[1]} {evr/timestamp[2]} {evr/timestamp[3]} {evr/timestamp[4]} {evr/timestamp[5]} {evr/timestamp[6]} {evr/timestamp[7]} {evr/timestamp[8]} {evr/timestamp[9]} {evr/timestamp[10]} {evr/timestamp[11]} {evr/timestamp[12]} {evr/timestamp[13]} {evr/timestamp[14]} {evr/timestamp[15]} {evr/timestamp[16]} {evr/timestamp[17]} {evr/timestamp[18]} {evr/timestamp[19]} {evr/timestamp[20]} {evr/timestamp[21]} {evr/timestamp[22]} {evr/timestamp[23]} {evr/timestamp[24]} {evr/timestamp[25]} {evr/timestamp[26]} {evr/timestamp[27]} {evr/timestamp[28]} {evr/timestamp[29]} {evr/timestamp[30]} {evr/timestamp[31]} {evr/timestamp[32]} {evr/timestamp[33]} {evr/timestamp[34]} {evr/timestamp[35]} {evr/timestamp[36]} {evr/timestamp[37]} {evr/timestamp[38]} {evr/timestamp[39]} {evr/timestamp[40]} {evr/timestamp[41]} {evr/timestamp[42]} {evr/timestamp[43]} {evr/timestamp[44]} {evr/timestamp[45]} {evr/timestamp[46]} {evr/timestamp[47]} {evr/timestamp[48]} {evr/timestamp[49]} {evr/timestamp[50]} {evr/timestamp[51]} {evr/timestamp[52]} {evr/timestamp[53]} {evr/timestamp[54]} {evr/timestamp[55]} {evr/timestamp[56]} {evr/timestamp[57]} {evr/timestamp[58]} {evr/timestamp[59]} {evr/timestamp[60]} {evr/timestamp[61]} {evr/timestamp[62]} {evr/timestamp[63]}]] +set_property port_width 2 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {adc_inst/adc_spi/state[0]} {adc_inst/adc_spi/state[1]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -set_property port_width 4 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {evr/prev_datastream[0]} {evr/prev_datastream[1]} {evr/prev_datastream[2]} {evr/prev_datastream[3]}]] +set_property port_width 16 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {adc_inst/adc_spi/spi_rdata[0]} {adc_inst/adc_spi/spi_rdata[1]} {adc_inst/adc_spi/spi_rdata[2]} {adc_inst/adc_spi/spi_rdata[3]} {adc_inst/adc_spi/spi_rdata[4]} {adc_inst/adc_spi/spi_rdata[5]} {adc_inst/adc_spi/spi_rdata[6]} {adc_inst/adc_spi/spi_rdata[7]} {adc_inst/adc_spi/spi_rdata[8]} {adc_inst/adc_spi/spi_rdata[9]} {adc_inst/adc_spi/spi_rdata[10]} {adc_inst/adc_spi/spi_rdata[11]} {adc_inst/adc_spi/spi_rdata[12]} {adc_inst/adc_spi/spi_rdata[13]} {adc_inst/adc_spi/spi_rdata[14]} {adc_inst/adc_spi/spi_rdata[15]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -set_property port_width 8 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {evr/myevent[0]} {evr/myevent[1]} {evr/myevent[2]} {evr/myevent[3]} {evr/myevent[4]} {evr/myevent[5]} {evr/myevent[6]} {evr/myevent[7]}]] +set_property port_width 9 [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {adc_inst/reg_o[idly_wval][0]} {adc_inst/reg_o[idly_wval][1]} {adc_inst/reg_o[idly_wval][2]} {adc_inst/reg_o[idly_wval][3]} {adc_inst/reg_o[idly_wval][4]} {adc_inst/reg_o[idly_wval][5]} {adc_inst/reg_o[idly_wval][6]} {adc_inst/reg_o[idly_wval][7]} {adc_inst/reg_o[idly_wval][8]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] -set_property port_width 1 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list evr/eventclock]] +set_property port_width 32 [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list {adc_inst/reg_o[spi_wdata][0]} {adc_inst/reg_o[spi_wdata][1]} {adc_inst/reg_o[spi_wdata][2]} {adc_inst/reg_o[spi_wdata][3]} {adc_inst/reg_o[spi_wdata][4]} {adc_inst/reg_o[spi_wdata][5]} {adc_inst/reg_o[spi_wdata][6]} {adc_inst/reg_o[spi_wdata][7]} {adc_inst/reg_o[spi_wdata][8]} {adc_inst/reg_o[spi_wdata][9]} {adc_inst/reg_o[spi_wdata][10]} {adc_inst/reg_o[spi_wdata][11]} {adc_inst/reg_o[spi_wdata][12]} {adc_inst/reg_o[spi_wdata][13]} {adc_inst/reg_o[spi_wdata][14]} {adc_inst/reg_o[spi_wdata][15]} {adc_inst/reg_o[spi_wdata][16]} {adc_inst/reg_o[spi_wdata][17]} {adc_inst/reg_o[spi_wdata][18]} {adc_inst/reg_o[spi_wdata][19]} {adc_inst/reg_o[spi_wdata][20]} {adc_inst/reg_o[spi_wdata][21]} {adc_inst/reg_o[spi_wdata][22]} {adc_inst/reg_o[spi_wdata][23]} {adc_inst/reg_o[spi_wdata][24]} {adc_inst/reg_o[spi_wdata][25]} {adc_inst/reg_o[spi_wdata][26]} {adc_inst/reg_o[spi_wdata][27]} {adc_inst/reg_o[spi_wdata][28]} {adc_inst/reg_o[spi_wdata][29]} {adc_inst/reg_o[spi_wdata][30]} {adc_inst/reg_o[spi_wdata][31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] -set_property port_width 1 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list evr/tbt_trig]] +set_property port_width 32 [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list {adc_inst/adc_spi/adc_spi_rdata[0]} {adc_inst/adc_spi/adc_spi_rdata[1]} {adc_inst/adc_spi/adc_spi_rdata[2]} {adc_inst/adc_spi/adc_spi_rdata[3]} {adc_inst/adc_spi/adc_spi_rdata[4]} {adc_inst/adc_spi/adc_spi_rdata[5]} {adc_inst/adc_spi/adc_spi_rdata[6]} {adc_inst/adc_spi/adc_spi_rdata[7]} {adc_inst/adc_spi/adc_spi_rdata[8]} {adc_inst/adc_spi/adc_spi_rdata[9]} {adc_inst/adc_spi/adc_spi_rdata[10]} {adc_inst/adc_spi/adc_spi_rdata[11]} {adc_inst/adc_spi/adc_spi_rdata[12]} {adc_inst/adc_spi/adc_spi_rdata[13]} {adc_inst/adc_spi/adc_spi_rdata[14]} {adc_inst/adc_spi/adc_spi_rdata[15]} {adc_inst/adc_spi/adc_spi_rdata[16]} {adc_inst/adc_spi/adc_spi_rdata[17]} {adc_inst/adc_spi/adc_spi_rdata[18]} {adc_inst/adc_spi/adc_spi_rdata[19]} {adc_inst/adc_spi/adc_spi_rdata[20]} {adc_inst/adc_spi/adc_spi_rdata[21]} {adc_inst/adc_spi/adc_spi_rdata[22]} {adc_inst/adc_spi/adc_spi_rdata[23]} {adc_inst/adc_spi/adc_spi_rdata[24]} {adc_inst/adc_spi/adc_spi_rdata[25]} {adc_inst/adc_spi/adc_spi_rdata[26]} {adc_inst/adc_spi/adc_spi_rdata[27]} {adc_inst/adc_spi/adc_spi_rdata[28]} {adc_inst/adc_spi/adc_spi_rdata[29]} {adc_inst/adc_spi/adc_spi_rdata[30]} {adc_inst/adc_spi/adc_spi_rdata[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] -set_property port_width 1 [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list evr/tbt_trig_i]] -create_debug_core u_ila_1 ila -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1] -set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1] -set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1] -set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1] -set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1] -set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1] -set_property C_TRIGIN_EN false [get_debug_cores u_ila_1] -set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1] -set_property port_width 1 [get_debug_ports u_ila_1/clk] -connect_debug_port u_ila_1/clk [get_nets [list evr/gth_txusr_clk]] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0] -set_property port_width 16 [get_debug_ports u_ila_1/probe0] -connect_debug_port u_ila_1/probe0 [get_nets [list {evr/gth_txdata_in[0]} {evr/gth_txdata_in[1]} {evr/gth_txdata_in[2]} {evr/gth_txdata_in[3]} {evr/gth_txdata_in[4]} {evr/gth_txdata_in[5]} {evr/gth_txdata_in[6]} {evr/gth_txdata_in[7]} {evr/gth_txdata_in[8]} {evr/gth_txdata_in[9]} {evr/gth_txdata_in[10]} {evr/gth_txdata_in[11]} {evr/gth_txdata_in[12]} {evr/gth_txdata_in[13]} {evr/gth_txdata_in[14]} {evr/gth_txdata_in[15]}]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1] -set_property port_width 8 [get_debug_ports u_ila_1/probe1] -connect_debug_port u_ila_1/probe1 [get_nets [list {evr/gth_txcharisk_in[0]} {evr/gth_txcharisk_in[1]} {evr/gth_txcharisk_in[2]} {evr/gth_txcharisk_in[3]} {evr/gth_txcharisk_in[4]} {evr/gth_txcharisk_in[5]} {evr/gth_txcharisk_in[6]} {evr/gth_txcharisk_in[7]}]] -create_debug_core u_ila_2 ila -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2] -set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2] -set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2] -set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2] -set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2] -set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2] -set_property C_TRIGIN_EN false [get_debug_cores u_ila_2] -set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2] -set_property port_width 1 [get_debug_ports u_ila_2/clk] -connect_debug_port u_ila_2/clk [get_nets [list system_i/zynq_ultra_ps_e_0/U0/pl_clk0]] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0] -set_property port_width 1 [get_debug_ports u_ila_2/probe0] -connect_debug_port u_ila_2/probe0 [get_nets [list evr/gth_cplllock]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1] -set_property port_width 1 [get_debug_ports u_ila_2/probe1] -connect_debug_port u_ila_2/probe1 [get_nets [list evr/gth_powergood]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2] -set_property port_width 1 [get_debug_ports u_ila_2/probe2] -connect_debug_port u_ila_2/probe2 [get_nets [list evr/gth_reset_rx_done]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3] -set_property port_width 1 [get_debug_ports u_ila_2/probe3] -connect_debug_port u_ila_2/probe3 [get_nets [list evr/gtwiz_reset_all_in]] +set_property port_width 32 [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list {adc_inst/adc_spi/adc_spi_wdata[0]} {adc_inst/adc_spi/adc_spi_wdata[1]} {adc_inst/adc_spi/adc_spi_wdata[2]} {adc_inst/adc_spi/adc_spi_wdata[3]} {adc_inst/adc_spi/adc_spi_wdata[4]} {adc_inst/adc_spi/adc_spi_wdata[5]} {adc_inst/adc_spi/adc_spi_wdata[6]} {adc_inst/adc_spi/adc_spi_wdata[7]} {adc_inst/adc_spi/adc_spi_wdata[8]} {adc_inst/adc_spi/adc_spi_wdata[9]} {adc_inst/adc_spi/adc_spi_wdata[10]} {adc_inst/adc_spi/adc_spi_wdata[11]} {adc_inst/adc_spi/adc_spi_wdata[12]} {adc_inst/adc_spi/adc_spi_wdata[13]} {adc_inst/adc_spi/adc_spi_wdata[14]} {adc_inst/adc_spi/adc_spi_wdata[15]} {adc_inst/adc_spi/adc_spi_wdata[16]} {adc_inst/adc_spi/adc_spi_wdata[17]} {adc_inst/adc_spi/adc_spi_wdata[18]} {adc_inst/adc_spi/adc_spi_wdata[19]} {adc_inst/adc_spi/adc_spi_wdata[20]} {adc_inst/adc_spi/adc_spi_wdata[21]} {adc_inst/adc_spi/adc_spi_wdata[22]} {adc_inst/adc_spi/adc_spi_wdata[23]} {adc_inst/adc_spi/adc_spi_wdata[24]} {adc_inst/adc_spi/adc_spi_wdata[25]} {adc_inst/adc_spi/adc_spi_wdata[26]} {adc_inst/adc_spi/adc_spi_wdata[27]} {adc_inst/adc_spi/adc_spi_wdata[28]} {adc_inst/adc_spi/adc_spi_wdata[29]} {adc_inst/adc_spi/adc_spi_wdata[30]} {adc_inst/adc_spi/adc_spi_wdata[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +set_property port_width 2 [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list {adc_inst/adc_spi/sclk[0]} {adc_inst/adc_spi/sclk[1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] +set_property port_width 2 [get_debug_ports u_ila_0/probe11] +connect_debug_port u_ila_0/probe11 [get_nets [list {adc_inst/adc_spi/sdi[0]} {adc_inst/adc_spi/sdi[1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] +set_property port_width 2 [get_debug_ports u_ila_0/probe12] +connect_debug_port u_ila_0/probe12 [get_nets [list {adc_inst/reg_o[fco_dlystr][0]} {adc_inst/reg_o[fco_dlystr][1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] +set_property port_width 16 [get_debug_ports u_ila_0/probe13] +connect_debug_port u_ila_0/probe13 [get_nets [list {adc_inst/reg_o[idly_wstr][0]} {adc_inst/reg_o[idly_wstr][1]} {adc_inst/reg_o[idly_wstr][2]} {adc_inst/reg_o[idly_wstr][3]} {adc_inst/reg_o[idly_wstr][4]} {adc_inst/reg_o[idly_wstr][5]} {adc_inst/reg_o[idly_wstr][6]} {adc_inst/reg_o[idly_wstr][7]} {adc_inst/reg_o[idly_wstr][8]} {adc_inst/reg_o[idly_wstr][9]} {adc_inst/reg_o[idly_wstr][10]} {adc_inst/reg_o[idly_wstr][11]} {adc_inst/reg_o[idly_wstr][12]} {adc_inst/reg_o[idly_wstr][13]} {adc_inst/reg_o[idly_wstr][14]} {adc_inst/reg_o[idly_wstr][15]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] +set_property port_width 1 [get_debug_ports u_ila_0/probe14] +connect_debug_port u_ila_0/probe14 [get_nets [list adc_inst/adc0_fco_mmcm_locked]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] +set_property port_width 1 [get_debug_ports u_ila_0/probe15] +connect_debug_port u_ila_0/probe15 [get_nets [list adc_inst/adc0_fco_mmcm_psdone]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] +set_property port_width 1 [get_debug_ports u_ila_0/probe16] +connect_debug_port u_ila_0/probe16 [get_nets [list adc_inst/adc1_fco_mmcm_locked]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] +set_property port_width 1 [get_debug_ports u_ila_0/probe17] +connect_debug_port u_ila_0/probe17 [get_nets [list adc_inst/adc1_fco_mmcm_psdone]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] +set_property port_width 1 [get_debug_ports u_ila_0/probe18] +connect_debug_port u_ila_0/probe18 [get_nets [list {adc_inst/reg_o[spi_we]}]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] diff --git a/src/hw/cstr/gth.xdc b/src/hw/cstr/gth.xdc index 494aaf7..4d89860 100644 --- a/src/hw/cstr/gth.xdc +++ b/src/hw/cstr/gth.xdc @@ -4,9 +4,9 @@ ## SI5347 OUT6 150MHz FMC_HPC0_GBTCLK_0 (MGT_229_REFCLK_0) set_property PACKAGE_PIN R28 [get_ports gth_evr_refclk_n] set_property PACKAGE_PIN R27 [get_ports gth_evr_refclk_p] -create_clock -period 3.2 -name clk_gth_evr_refclk_0 [get_ports gth_evr_refclk_p] +create_clock -period 3.200 -name clk_gth_evr_refclk_0 [get_ports gth_evr_refclk_p] ## SFP0 -set_property LOC GTHE4_CHANNEL_X0Y4 [get_cells evr/evr_syn.gth/inst/gen_gtwizard_gthe4_top.gth_wiz_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST] + diff --git a/src/hw/cstr/pins.xdc b/src/hw/cstr/pins.xdc index 6d912b4..76d6eb0 100644 --- a/src/hw/cstr/pins.xdc +++ b/src/hw/cstr/pins.xdc @@ -286,3 +286,4 @@ set_property SLEW FAST [get_ports {dbg[19]}] + diff --git a/src/hw/cstr/timing.xdc b/src/hw/cstr/timing.xdc index fbf7e48..69383ea 100644 --- a/src/hw/cstr/timing.xdc +++ b/src/hw/cstr/timing.xdc @@ -36,3 +36,4 @@ set_clock_groups -name adcclk_evrrxclk -asynchronous -group [get_clocks -of_obje + diff --git a/src/hw/hdl/adc_ltc2195.vhd b/src/hw/hdl/adc_ltc2195.vhd index e581aa5..0415c4b 100644 --- a/src/hw/hdl/adc_ltc2195.vhd +++ b/src/hw/hdl/adc_ltc2195.vhd @@ -147,18 +147,18 @@ end component; signal adc_fifo_empty : std_logic_vector(3 downto 0); --- attribute mark_debug : string; --- attribute mark_debug of reg_o: signal is "true"; + attribute mark_debug : string; + attribute mark_debug of reg_o: signal is "true"; -- attribute mark_debug of reg_i: signal is "true"; -- attribute mark_debug of adca_data: signal is "true"; -- attribute mark_debug of adcb_data: signal is "true"; -- attribute mark_debug of adcc_data: signal is "true"; -- attribute mark_debug of adcd_data: signal is "true"; -- attribute mark_debug of adc_data: signal is "true"; --- attribute mark_debug of adc0_fco_mmcm_psdone: signal is "true"; --- attribute mark_debug of adc0_fco_mmcm_locked: signal is "true"; --- attribute mark_debug of adc1_fco_mmcm_psdone: signal is "true"; --- attribute mark_debug of adc1_fco_mmcm_locked: signal is "true"; + attribute mark_debug of adc0_fco_mmcm_psdone: signal is "true"; + attribute mark_debug of adc0_fco_mmcm_locked: signal is "true"; + attribute mark_debug of adc1_fco_mmcm_psdone: signal is "true"; + attribute mark_debug of adc1_fco_mmcm_locked: signal is "true"; @@ -316,7 +316,7 @@ adc_chd: entity work.adc_s2p ); --sync both adc's to adc0_fco_mmcm for now. -adc_clk_out <= adc1_fco_mmcm; +adc_clk_out <= adc0_fco_mmcm; --process(adc_clk_out) diff --git a/src/hw/hdl/evr/evr_top.vhd b/src/hw/hdl/evr/evr_top.vhd index 6da595d..303e4b8 100644 --- a/src/hw/hdl/evr/evr_top.vhd +++ b/src/hw/hdl/evr/evr_top.vhd @@ -59,8 +59,8 @@ entity evr_top is gps_trig : out std_logic; timestamp : out std_logic_vector(63 downto 0); - evr_rcvd_clk : out std_logic; - evr_ref_clk : out std_logic + evr_rcvd_clk : out std_logic + ); @@ -169,8 +169,6 @@ end component; signal gth_cplllock : std_logic; signal gth_cpllrefclklost : std_logic; - signal gth_refclk_odiv2 : std_logic; - signal gth_userclk_tx_srcclk : std_logic; signal gth_userclk_tx_usrclk : std_logic; signal gth_userclk_tx_usrclk2 : std_logic; @@ -219,7 +217,6 @@ end component; attribute mark_debug : string; - attribute mark_debug of reg_o: signal is "true"; attribute mark_debug of gth_txdata_in: signal is "true"; attribute mark_debug of gth_txcharisk_in: signal is "true"; attribute mark_debug of gth_rx_userdata: signal is "true"; @@ -244,7 +241,6 @@ end component; begin evr_rcvd_clk <= gth_rxusr_clk; -evr_ref_clk <= '0'; @@ -256,7 +252,7 @@ refclk0_buf : IBUFDS_GTE4 ) port map ( O => gth_refclk, -- 1-bit output: Refer to Transceiver User Guide - ODIV2 => open, -- 1-bit output: Refer to Transceiver User Guide + ODIV2 => open, --gth_refclk_odiv2, -- 1-bit output: Refer to Transceiver User Guide CEB => '0', -- 1-bit input: Refer to Transceiver User Guide I => gth_refclk_p, -- 1-bit input: Refer to Transceiver User Guide IB => gth_refclk_n -- 1-bit input: Refer to Transceiver User Guide @@ -265,7 +261,7 @@ refclk0_buf : IBUFDS_GTE4 --for debug, sends refclk to debug header --BUFG_GT_refclk : BUFG_GT -- port map ( --- O => evr_ref_clk, -- 1-bit output: Buffer +-- O => gth_refclk_buf, -- 1-bit output: Buffer -- CE => '1', -- 1-bit input: Buffer enable -- CEMASK => '0', -- 1-bit input: CE Mask -- CLR => '0', --gth_reset(0), -- 1-bit input: Asynchronous clear @@ -307,7 +303,7 @@ BUFG_GT_rx : BUFG_GT O => gth_rxusr_clk, -- 1-bit output: Buffer CE => '1', -- 1-bit input: Buffer enable CEMASK => '0', -- 1-bit input: CE Mask - CLR => '0', --reg_o.reset, --gth_reset(0), -- 1-bit input: Asynchronous clear + CLR => reg_o.reset, --gth_reset(0), -- 1-bit input: Asynchronous clear CLRMASK => '0', -- 1-bit input: CLR Mask DIV => "000", -- 3-bit input: Dynamic divide Value I => gth_rxout_clk -- 1-bit input: Buffer @@ -318,7 +314,7 @@ BUFG_GT_tx : BUFG_GT O => gth_txusr_clk, -- 1-bit output: Buffer CE => '1', -- 1-bit input: Buffer enable CEMASK => '0', -- 1-bit input: CE Mask - CLR => '0', --reg_o.reset, --gth_reset(0), -- 1-bit input: Asynchronous clear + CLR => reg_o.reset, --gth_reset(0), -- 1-bit input: Asynchronous clear CLRMASK => '0', -- 1-bit input: CLR Mask DIV => "000", -- 3-bit input: Dynamic divide Value I => gth_txout_clk -- 1-bit input: Buffer diff --git a/src/hw/hdl/ltc2195_spi.vhd b/src/hw/hdl/ltc2195_spi.vhd index e5a75f5..ea0e624 100644 --- a/src/hw/hdl/ltc2195_spi.vhd +++ b/src/hw/hdl/ltc2195_spi.vhd @@ -66,17 +66,17 @@ architecture rtl of ltc2195_spi is signal rwbit : std_logic; signal adc_sel : std_logic; --- attribute mark_debug : string; --- attribute mark_debug of bcnt: signal is "true"; --- attribute mark_debug of state: signal is "true"; --- attribute mark_debug of adc_spi_wdata: signal is "true"; --- attribute mark_debug of adc_spi_rdata: signal is "true"; --- attribute mark_debug of spi_wdata: signal is "true"; --- attribute mark_debug of spi_rdata: signal is "true"; --- attribute mark_debug of sclk: signal is "true"; --- attribute mark_debug of sdi: signal is "true"; --- attribute mark_debug of sdo: signal is "true"; --- attribute mark_debug of csb: signal is "true"; + attribute mark_debug : string; + attribute mark_debug of bcnt: signal is "true"; + attribute mark_debug of state: signal is "true"; + attribute mark_debug of adc_spi_wdata: signal is "true"; + attribute mark_debug of adc_spi_rdata: signal is "true"; + attribute mark_debug of spi_wdata: signal is "true"; + attribute mark_debug of spi_rdata: signal is "true"; + attribute mark_debug of sclk: signal is "true"; + attribute mark_debug of sdi: signal is "true"; + attribute mark_debug of sdo: signal is "true"; + attribute mark_debug of csb: signal is "true"; @@ -150,7 +150,7 @@ process (sys_clk, reset) when CLKP2 => -- CLKP2 clock phase HIGH sclk <= "11"; - if (adc_sel = '1') then + if (adc_sel = '0') then spi_rdata(bcnt) <= sdo(0); else spi_rdata(bcnt) <= sdo(1); diff --git a/src/hw/hdl/top.vhd b/src/hw/hdl/top.vhd index 6be9ecd..59a7aa6 100644 --- a/src/hw/hdl/top.vhd +++ b/src/hw/hdl/top.vhd @@ -225,7 +225,7 @@ dbg(19) <= fp_in(3); fp_out(0) <= pl_clk0; fp_out(1) <= evr_rcvd_clk; --pl_clk1; --adc_clk_in; fp_out(2) <= adc_clk; -fp_out(3) <= evr_ref_clk; --tbt_trig; +fp_out(3) <= tbt_trig; fp_led(7) <= dma_adc_active; fp_led(6) <= dma_tbt_active; @@ -477,8 +477,7 @@ evr: entity work.evr_top usr_trig => evr_dma_trig, gps_trig => evr_gps_trig, timestamp => evr_ts, - evr_rcvd_clk => evr_rcvd_clk, - evr_ref_clk => evr_ref_clk + evr_rcvd_clk => evr_rcvd_clk ); @@ -504,7 +503,8 @@ ps_pl: entity work.ps_io reg_i_dma => reg_i_dma, reg_o_dsa => reg_o_dsa, reg_o_pll => reg_o_pll, - reg_i_pll => reg_i_pll + reg_i_pll => reg_i_pll, + reg_o_evr => reg_o_evr ); diff --git a/src/hw/tcl/adc_fifo.tcl b/src/hw/tcl/adc_fifo.tcl new file mode 100644 index 0000000..fe6c56c --- /dev/null +++ b/src/hw/tcl/adc_fifo.tcl @@ -0,0 +1,11 @@ +create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name adc_fifo +set_property -dict [list \ + CONFIG.Component_Name {adc_fifo} \ + CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM} \ + CONFIG.Input_Data_Width {16} \ + CONFIG.Input_Depth {2048} \ + CONFIG.Performance_Options {First_Word_Fall_Through} \ + CONFIG.Reset_Pin {false} \ + CONFIG.Use_Extra_Logic {true} \ + CONFIG.asymmetric_port_width {false} \ +] [get_ips adc_fifo] diff --git a/src/sw/inc/psc_msg.h b/src/sw/inc/psc_msg.h index 4323d2e..e4a4e61 100644 --- a/src/sw/inc/psc_msg.h +++ b/src/sw/inc/psc_msg.h @@ -139,6 +139,8 @@ typedef struct StatusMsg { #define FP_LED_MSG1 4 #define PILOT_TONE_ENB_MSG1 8 #define ADC_IDLY_MSG1 12 +#define ADC_MMCM0_MSG1 16 +#define ADC_MMCM1_MSG1 20 #define DMA_TRIG_SRC_MSG1 52 #define DMA_ADCLEN_MSG1 56 #define DMA_TBTLEN_MSG1 60 diff --git a/src/sw/src/ltc2195_init.c b/src/sw/src/ltc2195_init.c index 58a7731..c99dacc 100644 --- a/src/sw/src/ltc2195_init.c +++ b/src/sw/src/ltc2195_init.c @@ -14,7 +14,7 @@ void ltc2195_init() { - int i, regAddr, regVal; + s32 i, regAddr, regVal, rdbk; s16 cha, chb, chc, chd; xil_printf("Programming LTC2195 (ADC)... "); @@ -24,12 +24,57 @@ void ltc2195_init() //set 2's complement regAddr = 1; regVal = 0x20; + xil_printf("Setting SPI Register\r\n"); + xil_printf("SPI Write Reg 1 to 0x20\r\n"); Xil_Out32(XPAR_M_AXI_BASEADDR + ADC_SPI_REG, regAddr<<8 | regVal); usleep(1000); + //read back from adc0 + Xil_Out32(XPAR_M_AXI_BASEADDR + ADC_SPI_REG, 0x8000 | regAddr<<8 | regVal); + usleep(1000); + rdbk = Xil_In32(XPAR_M_AXI_BASEADDR + ADC_SPI_REG); + xil_printf("SPI Read Back ADC0 Reg 1 = %x\r\n",rdbk); + //read back from adc1 + Xil_Out32(XPAR_M_AXI_BASEADDR + ADC_SPI_REG, 0x10000 | 0x8000 | regAddr<<8 | regVal); + usleep(1000); + rdbk = Xil_In32(XPAR_M_AXI_BASEADDR + ADC_SPI_REG); + xil_printf("SPI Read Back ADC1 Reg 1 = %x\r\n",rdbk); + + + //set test pattern + regAddr = 3; + regVal = 0x01; + Xil_Out32(XPAR_M_AXI_BASEADDR + ADC_SPI_REG, regAddr<<8 | regVal); + usleep(1000); + //read back + Xil_Out32(XPAR_M_AXI_BASEADDR + ADC_SPI_REG, 0x8000 | regAddr<<8 | regVal); + usleep(1000); + rdbk = Xil_In32(XPAR_M_AXI_BASEADDR + ADC_SPI_REG); + xil_printf("SPI Write Reg 3 to 0x55\r\n"); + xil_printf("SPI Read Back Reg 3 = %x\r\n",rdbk); + + //set test pattern + regAddr = 4; + regVal = 0x00; + xil_printf("SPI Write Reg 4 to 0x55\r\n"); + Xil_Out32(XPAR_M_AXI_BASEADDR + ADC_SPI_REG, regAddr<<8 | regVal); + usleep(1000); + //read back + Xil_Out32(XPAR_M_AXI_BASEADDR + ADC_SPI_REG, 0x8000 | regAddr<<8 | regVal); + usleep(1000); + rdbk = Xil_In32(XPAR_M_AXI_BASEADDR + ADC_SPI_REG); + xil_printf("SPI Read Back ADC0 Reg 4 = %x\r\n",rdbk); + Xil_Out32(XPAR_M_AXI_BASEADDR + ADC_SPI_REG, 0x10000 | 0x8000 | regAddr<<8 | regVal); + usleep(1000); + rdbk = Xil_In32(XPAR_M_AXI_BASEADDR + ADC_SPI_REG); + xil_printf("SPI Read Back ADC0 Reg 4 = %x\r\n",rdbk); + + + + //set 4 lane output regAddr = 2; - regVal = 1; + regVal = 1; //set to 1 for normal, set to 5 for test pattern Xil_Out32(XPAR_M_AXI_BASEADDR + ADC_SPI_REG, regAddr<<8 | regVal); //fpgabase[ADC_SPI_REG] = regAddr<<8 | regVal; usleep(1000); @@ -41,14 +86,20 @@ void ltc2195_init() Xil_Out32(XPAR_M_AXI_BASEADDR + ADC_IDLYSTR_REG, 0); + + + + + + //read and print 20 ADC samples - for (i=0;i<10;i++) { + for (i=0;i<20;i++) { cha = (s16) Xil_In16(XPAR_M_AXI_BASEADDR + ADC_RAWCHA_REG); chb = (s16) Xil_In16(XPAR_M_AXI_BASEADDR + ADC_RAWCHB_REG); chc = (s16) Xil_In16(XPAR_M_AXI_BASEADDR + ADC_RAWCHC_REG); chd = (s16) Xil_In16(XPAR_M_AXI_BASEADDR + ADC_RAWCHD_REG); - xil_printf("%d\t%d\t%d\t%d\r\n",cha,chb,chc,chd); + xil_printf("%x\t%x\t%x\t%x\r\n",cha,chb,chc,chd); usleep(100000); } diff --git a/src/sw/src/main.c b/src/sw/src/main.c index 057c45c..5e075b1 100644 --- a/src/sw/src/main.c +++ b/src/sw/src/main.c @@ -30,6 +30,12 @@ #define DEFAULT_IP_MASK "255.255.255.0" #define DEFAULT_GW_ADDRESS "10.0.142.1" +//#define DEFAULT_IP_ADDRESS "130.199.104.34" +//#define DEFAULT_IP_MASK "255.255.254.0" +//#define DEFAULT_GW_ADDRESS "130.199.104.24" + + + #define DELAY_100_MS 100UL #define DELAY_1_SECOND (10*DELAY_100_MS) diff --git a/src/sw/src/psc_control_thread.c b/src/sw/src/psc_control_thread.c index 2954b44..fb1bd1d 100644 --- a/src/sw/src/psc_control_thread.c +++ b/src/sw/src/psc_control_thread.c @@ -341,10 +341,24 @@ void psc_control_thread() xil_printf("ChC IDLY rval=%d\r\n",rdval); rdval = Xil_In32(XPAR_M_AXI_BASEADDR + ADC_IDLYCHDRVAL_REG); xil_printf("ChD IDLY rval=%d\r\n",rdval); + break; - break; + case ADC_MMCM0_MSG1: + if (MsgData == 1) { + xil_printf("Setting ADC0 MMCM FCO Delay\r\n"); + Xil_Out32(XPAR_M_AXI_BASEADDR + ADC_FCOMMCM_REG, 1); + Xil_Out32(XPAR_M_AXI_BASEADDR + ADC_FCOMMCM_REG, 0); + } + break; + case ADC_MMCM1_MSG1: + if (MsgData == 1) { + xil_printf("Setting ADC1 MMCM FCO Delay\r\n"); + Xil_Out32(XPAR_M_AXI_BASEADDR + ADC_FCOMMCM_REG, 2); + Xil_Out32(XPAR_M_AXI_BASEADDR + ADC_FCOMMCM_REG, 0); + } + break; default: xil_printf("Msg not supported yet...\r\n"); diff --git a/vivado.jou b/vivado.jou new file mode 100644 index 0000000..fda4371 --- /dev/null +++ b/vivado.jou @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Vivado v2022.2 (64-bit) +# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022 +# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 +# Start of session at: Thu Oct 31 16:12:19 2024 +# Process ID: 4796 +# Current directory: /home/mead/rfbpm/fwk/zubpm +# Command line: vivado +# Log file: /home/mead/rfbpm/fwk/zubpm/vivado.log +# Journal file: /home/mead/rfbpm/fwk/zubpm/vivado.jou +# Running On: mead-home, OS: Linux, CPU Frequency: 4988.856 MHz, CPU Physical cores: 8, Host memory: 33586 MB +#----------------------------------------------------------- +start_gui