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Fix LPDDR5; update tests
1 parent 5a299e8 commit 88be8a0

10 files changed

+40
-23
lines changed

‎.gitignore

+2
Original file line numberDiff line numberDiff line change
@@ -43,3 +43,5 @@ build*/
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bin/
4444
*.swp
4545
.~*
46+
cmake-build-debug
47+
cmake-build-release

‎src/DRAMPower/DRAMPower/standards/lpddr5/calculation_LPDDR5.cpp

+9-10
Original file line numberDiff line numberDiff line change
@@ -79,16 +79,15 @@ namespace DRAMPower {
7979
auto IBeta = dram.memSpec.memPowerSpec[vd].iBeta;
8080

8181
auto I_rho = rho * (IDD3N - IDD2N) + IDD2N;
82-
auto I_1 = (1.0 / B) * (IDD3N + (B - 1) * (rho * (IDD3N - IDD2N) + IDD2N));
83-
auto I_2 = I_1 + (I_1 - I_rho);
82+
auto I_2 = IDD3N + (IDD3N - I_rho);
8483
auto I_theta = (IDD_0 * (t_RP + t_RAS) - IBeta * t_RP) * (1 / t_RAS);
8584
auto IDD5PB_B = (IDD5PB * (t_REFI / 8) - IDD2N * ((t_REFI / 8) - t_RFCPB)) * (1.0 / t_RFCPB);
86-
auto approx_IDD3N = I_rho + B * (I_1 - I_rho);
85+
auto approx_IDD3N = I_rho + B * (IDD3N - I_rho);
8786

8887
for (std::size_t b = 0; b < dram.memSpec.numberOfBanks; ++b) {
8988
const auto &bank = stats.bank[b];
9089

91-
energy.bank_energy[b].E_act += E_act(VDD, I_theta, I_1, t_RAS, bank.counter.act);
90+
energy.bank_energy[b].E_act += E_act(VDD, I_theta, IDD3N, t_RAS, bank.counter.act);
9291
energy.bank_energy[b].E_pre += E_pre(VDD, IBeta, IDD2N, t_RP, bank.counter.pre);
9392
energy.bank_energy[b].E_bg_act += E_BG_act_star(B, VDD, approx_IDD3N, I_rho,stats.bank[b].cycles.activeTime() * t_CK);
9493
energy.bank_energy[b].E_bg_pre += E_BG_pre(B, VDD, IDD2N, stats.total.cycles.pre * t_CK);
@@ -98,15 +97,15 @@ namespace DRAMPower {
9897
energy.bank_energy[b].E_RDA += E_RD(VDD, IDD4R, I_2, BL, DR, t_WCK, bank.counter.readAuto);
9998
energy.bank_energy[b].E_WRA += E_WR(VDD, IDD4W, I_2, BL, DR, t_WCK, bank.counter.writeAuto);
10099
} else {
101-
energy.bank_energy[b].E_RD += E_RD(VDD, IDD4R, I_1, BL, DR, t_WCK, bank.counter.reads);
102-
energy.bank_energy[b].E_WR += E_WR(VDD, IDD4W, I_1, BL, DR, t_WCK, bank.counter.writes);
103-
energy.bank_energy[b].E_RDA += E_RD(VDD, IDD4R, I_1, BL, DR, t_WCK, bank.counter.readAuto);
104-
energy.bank_energy[b].E_WRA += E_WR(VDD, IDD4W, I_1, BL, DR, t_WCK, bank.counter.writeAuto);
100+
energy.bank_energy[b].E_RD += E_RD(VDD, IDD4R, IDD3N, BL, DR, t_WCK, bank.counter.reads);
101+
energy.bank_energy[b].E_WR += E_WR(VDD, IDD4W, IDD3N, BL, DR, t_WCK, bank.counter.writes);
102+
energy.bank_energy[b].E_RDA += E_RD(VDD, IDD4R, IDD3N, BL, DR, t_WCK, bank.counter.readAuto);
103+
energy.bank_energy[b].E_WRA += E_WR(VDD, IDD4W, IDD3N, BL, DR, t_WCK, bank.counter.writeAuto);
105104
}
106105
energy.bank_energy[b].E_pre_RDA += E_pre(VDD, IBeta, IDD2N, t_RP, bank.counter.readAuto);
107106
energy.bank_energy[b].E_pre_WRA += E_pre(VDD, IBeta, IDD2N, t_RP, bank.counter.writeAuto);
108-
energy.bank_energy[b].E_ref_AB += E_ref_ab(B, VDD, IDD5, IDD3N, t_RFC, bank.counter.refAllBank);
109-
energy.bank_energy[b].E_ref_PB += E_ref_pb(VDD, IDD5PB_B, I_1, t_RFCPB, bank.counter.refPerBank);
107+
energy.bank_energy[b].E_ref_AB += E_ref_ab(B, VDD, IDD5, approx_IDD3N, t_RFC, bank.counter.refAllBank);
108+
energy.bank_energy[b].E_ref_PB += E_ref_pb(VDD, IDD5PB_B, IDD3N, t_RFCPB, bank.counter.refPerBank);
110109
energy.bank_energy[b].E_ref_2B += E_ref_p2b(VDD, IDD5PB_B, I_2, t_RFCPB, bank.counter.refPerTwoBanks);
111110
}
112111

‎tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_14.cpp

+4-2
Original file line numberDiff line numberDiff line change
@@ -41,8 +41,10 @@ class DramPowerTest_LPDDR5_14 : public ::testing::Test {
4141
memSpec.numberOfBanks = 8;
4242
memSpec.banksPerGroup = 8;
4343
memSpec.numberOfBankGroups = 1;
44-
45-
memSpec.memTimingSpec.tRAS = 20;
44+
memSpec.BGroupMode = false;
45+
46+
47+
memSpec.memTimingSpec.tRAS = 20;
4648
memSpec.memTimingSpec.tRTP = 10;
4749
memSpec.memTimingSpec.tWR = 11;
4850
memSpec.memTimingSpec.tWL = 0;

‎tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_15.cpp

+4-2
Original file line numberDiff line numberDiff line change
@@ -35,8 +35,10 @@ class DramPowerTest_LPDDR5_15 : public ::testing::Test {
3535
memSpec.numberOfBanks = 8;
3636
memSpec.banksPerGroup = 8;
3737
memSpec.numberOfBankGroups = 1;
38-
39-
memSpec.memTimingSpec.tRAS = 10;
38+
memSpec.BGroupMode = false;
39+
40+
41+
memSpec.memTimingSpec.tRAS = 10;
4042
memSpec.memTimingSpec.tRTP = 10;
4143
memSpec.memTimingSpec.tWR = 20;
4244

‎tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_16.cpp

+4-2
Original file line numberDiff line numberDiff line change
@@ -37,8 +37,10 @@ class DramPowerTest_LPDDR5_16 : public ::testing::Test {
3737
memSpec.numberOfBanks = 8;
3838
memSpec.banksPerGroup = 8;
3939
memSpec.numberOfBankGroups = 1;
40-
41-
memSpec.memTimingSpec.tRAS = 10;
40+
memSpec.BGroupMode = false;
41+
42+
43+
memSpec.memTimingSpec.tRAS = 10;
4244
memSpec.memTimingSpec.tRTP = 10;
4345
memSpec.memTimingSpec.tRFCPB = 25;
4446
memSpec.memTimingSpec.tWR = 20;

‎tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_17.cpp

+4-2
Original file line numberDiff line numberDiff line change
@@ -31,8 +31,10 @@ class DramPowerTest_LPDDR5_17 : public ::testing::Test {
3131
memSpec.numberOfBanks = 8;
3232
memSpec.numberOfBankGroups = 2;
3333
memSpec.perTwoBankOffset = 2;
34-
35-
memSpec.memTimingSpec.tRAS = 10;
34+
memSpec.BGroupMode = true;
35+
36+
37+
memSpec.memTimingSpec.tRAS = 10;
3638
memSpec.memTimingSpec.tRTP = 10;
3739
memSpec.memTimingSpec.tRFCPB = 25;
3840

‎tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_18.cpp

+3-1
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,10 @@ class DramPowerTest_LPDDR5_18 : public ::testing::Test {
3434
memSpec.numberOfBankGroups = 2;
3535
memSpec.banksPerGroup = 4;
3636
memSpec.perTwoBankOffset = 2;
37+
memSpec.BGroupMode = true;
3738

38-
memSpec.memTimingSpec.tRAS = 10;
39+
40+
memSpec.memTimingSpec.tRAS = 10;
3941
memSpec.memTimingSpec.tRTP = 10;
4042
memSpec.memTimingSpec.tRCD = 20;
4143
memSpec.memTimingSpec.tRFC = 25;

‎tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_19.cpp

+4-2
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,10 @@ class DramPowerTest_LPDDR5_19 : public ::testing::Test {
3434
memSpec.numberOfBanks = 8;
3535
memSpec.numberOfBankGroups = 2;
3636
memSpec.banksPerGroup = 4;
37-
38-
memSpec.memTimingSpec.tRAS = 10;
37+
memSpec.BGroupMode = true;
38+
39+
40+
memSpec.memTimingSpec.tRAS = 10;
3941
memSpec.memTimingSpec.tRTP = 10;
4042
memSpec.memTimingSpec.tRCD = 20;
4143
memSpec.memTimingSpec.tRFC = 25;

‎tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_20.cpp

+4-2
Original file line numberDiff line numberDiff line change
@@ -32,8 +32,10 @@ class DramPowerTest_LPDDR5_20 : public ::testing::Test {
3232
memSpec.numberOfBanks = 8;
3333
memSpec.numberOfBankGroups = 2;
3434
memSpec.banksPerGroup = 4;
35-
36-
memSpec.memTimingSpec.tRAS = 10;
35+
memSpec.BGroupMode = true;
36+
37+
38+
memSpec.memTimingSpec.tRAS = 10;
3739
memSpec.memTimingSpec.tRTP = 10;
3840
memSpec.memTimingSpec.tRCD = 20;
3941
memSpec.memTimingSpec.tRFC = 25;

‎tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_21.cpp

+2
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,8 @@ class DramPowerTest_LPDDR5_21 : public ::testing::Test {
3333
memSpec.numberOfBanks = 8;
3434
memSpec.numberOfBankGroups = 2;
3535
memSpec.banksPerGroup = 4;
36+
memSpec.BGroupMode = true;
37+
3638

3739
memSpec.memTimingSpec.tRAS = 10;
3840
memSpec.memTimingSpec.tRTP = 10;

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