applet.interface.uart: high Baud rates drop data

[attie]

It seems that using ~1.5Mbaud, with high Rx data rates can cause the applet FIFOs to overflow, and silently drop data.

1.5Mbaud is worst-case of ~150KB/s... this overflow is likely due to the relatively inefficient USB utilization that is incurred with the default auto_flush=True.

Suggestions:

1. Set auto_flush=False, and implement a timer to flush buffers after a number of idle bit/word-times
2. Increase FPGA-side FIFO size, past the default of depth=512
3. Add a register to indicate overflow / dropped frames

I think that this should be a non-issue for Tx data, as the buffers will back up, eventually into Python.

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This was discovered by @marcan while working on Asahi Linux.

[whitequark]

We should probably implement something like Nagle for UART.