AULA 9

Added Aula 9 / Class 9, derived from Class 8, mini-calculator, operation
selection, shift register left/right (multiplication)

Author: GSimas

AULA9/C1.vhd

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+library IEEE;
+use IEEE.Std_Logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity C1 is
+port (A: in std_logic_vector(7 downto 0);
+		B: in std_logic_vector(7 downto 0);
+		F: out std_logic_vector(7 downto 0)
+		);
+end C1;
+
+architecture circuito of C1 is
+begin
+	F <= A + B;
+end circuito;

AULA9/C2.vhd

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+library IEEE;
+use IEEE.Std_Logic_1164.all;
+
+entity C2 is
+port (A: in std_logic_vector(7 downto 0);
+		B: in std_logic_vector(7 downto 0);
+		F: out std_logic_vector(7 downto 0)
+		);
+end C2;
+
+architecture circuito of C2 is
+begin
+		F <= A or B;
+end circuito;

AULA9/C3.vhd

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+library IEEE;
+use IEEE.Std_Logic_1164.all;
+
+entity desloc_1_bit_esq is
+	port(	CLK: in std_logic;
+			ENABLE : in std_logic;
+			RST: in std_logic;
+			sr_in: in std_logic_vector(7 downto 0);
+			sr_out: out std_logic_vector(7 downto 0)
+			);
+end entity;
+
+architecture rtl of desloc_1_bit_esq is
+signal sr: std_logic_vector (7 downto 0); -- Registrador de N bits
+
+begin
+	process (CLK, RST)
+	begin
+		if (RST = '0') then	-- Reset assíncrono do registrador
+			sr <= (others => '0');
+		elsif (rising_edge(CLK)) then -- Sinal de clock do registrador (subida)
+			if (ENABLE = '1') then		-- Sinal de enable do registrador
+				sr(7 downto 1) <= sr_in(6 downto 0);-- Desloca 1 bit para a esquerda. Bit mais significativo é perdido.
+				sr(0) <= '0';
+			end if;
+		end if;
+	end process;
+	sr_out <= sr;
+end rtl;
+

AULA9/C3.vhd.bak

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+library IEEE;
+use IEEE.Std_Logic_1164.all;
+
+entity C3 is
+port (A: in std_logic_vector(7 downto 0);
+		B: in std_logic_vector(7 downto 0);
+		F: out std_logic_vector(7 downto 0)
+		);
+end C3;
+
+architecture circuito of C3 is
+begin
+	F <= A xor B;
+end circuito;

AULA9/C4.vhd

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+library IEEE;
+use IEEE.Std_Logic_1164.all;
+
+entity desloc_1_bit_dir is
+	generic(N: natural := 64);
+	port(	CLK: in std_logic;
+			ENABLE : in std_logic;
+			RST: in std_logic;
+			sr_in: in std_logic_vector(7 downto 0);
+			sr_out: out std_logic_vector(7 downto 0)
+			);
+end entity;
+
+architecture rtl of desloc_1_bit_dir is
+signal sr: std_logic_vector (7 downto 0); -- Registrador de N bits
+
+begin
+	process (CLK, RST)
+	begin
+		if (RST = '0') then	-- Reset assíncrono do registrador
+			sr <= (others => '0');
+		elsif (rising_edge(CLK)) then -- Sinal de clock do registrador (subida)
+			if (ENABLE = '1') then		-- Sinal de enable do registrador
+				sr(6 downto 0) <= sr_in(7 downto 1);-- Desloca 1 bit para a direita. Bit menos significativo é perdido.
+				sr(7) <= '1';
+			end if;
+		end if;
+	end process;
+	sr_out <= sr;
+end rtl;

AULA9/C4.vhd.bak

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+library IEEE;
+use IEEE.Std_Logic_1164.all;
+
+entity C4 is
+port (A: in std_logic_vector(7 downto 0);
+		B: in std_logic_vector(7 downto 0);
+		F: out std_logic_vector(7 downto 0)
+		);
+end C4;
+
+architecture circuito of C4 is
+begin
+		F <= not(A);
+end circuito;

AULA9/FSMctrl.vhd

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+library IEEE;
+use ieee.std_logic_1164.all;
+
+-- ENTITY
+
+entity FSMctrl is
+port(
+	CLK, RST, ENTER: in std_logic;
+	Operacao: in std_logic_vector(1 downto 0);
+	Selecao: out std_logic_vector(1 downto 0);
+	Enable_1, Enable_2: out std_logic
+	);
+end FSMctrl;
+
+
+--ARCHITECTURE
+
+architecture FSM_beh of FSMctrl is
+	type states is(S0,S1,S2,S3,S4,S5,S6,S7);
+	signal EA, PE: states;
+	signal clock: std_logic;
+	signal reset: std_logic;
+	
+begin
+
+	clock <= CLK;
+	
+	P1: process(clock, reset)
+	begin
+		if reset = '0' then
+			EA <= S0;
+		elsif clock'event and clock = '1' then
+			EA <= PE;
+		end if;
+	end process;
+	
+	P2: process(EA, ENTER, Operacao)
+	begin
+		case EA is
+		
+			when S0 =>
+				if Enter = '1' then
+					PE <= S0;
+				else
+					PE <= S1;
+				end if;
+				Enable_1 <= '0';
+				Enable_2 <= '0';
+				
+			when S1 =>
+				if Enter = '0' then
+					PE <= S1;
+				else
+					PE <= S2;
+				end if;
+				Enable_1 <= '1';
+				Enable_2 <= '0';
+			
+			when S2 =>
+				Enable_1 <= '0';
+				Enable_2 <= '0';
+				if Operacao = "00" then
+					PE <= S3;
+				elsif Operacao = "01" then
+					PE <= S4;
+				elsif Operacao = "10" then
+					PE <= S5;
+				elsif Operacao = "11" then
+					PE <= S6;
+				end if;
+				
+			when S3 =>
+				Selecao <= "00";
+				if Enter = '1' then
+					PE <= S3;
+				else
+					PE <= S7;
+				end if;
+				
+			when S4 =>
+				Selecao <= "01";
+				if Enter = '1' then
+					PE <= S4;
+				else
+					PE <= S7;
+				end if;
+			
+			when S5 =>
+				Enable_1 <= '1';
+				Enable_2 <= '1';
+				Selecao <= "10";
+				PE <= S0;
+			   
+			when S6 =>
+				Enable_1 <= '1';
+				Enable_2 <= '1';
+				Selecao <= "11";
+				PE <= S0;
+			
+			when S7 =>
+				Enable_1 <= '0';
+				Enable_2 <= '1';
+				PE <= S0; 
+			
+		end case;
+	end process;
+end FSM_beh;
+	
+	
+	
+	

AULA9/FSMctrl.vhd.bak

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+library IEEE;
+use ieee.std_logic_1164.all;
+
+-- ENTITY
+
+entity FSMctrl is
+port(
+	CLK, RST, ENTER: in std_logic;
+	Operacao: in std_logic_vector(1 downto 0);
+	Selecao: out std_logic_vector(1 downto 0);
+	Enable_1, Enable_2: out std_logic
+	);
+end FSMctrl;
+
+
+--ARCHITECTURE
+
+architecture FSM_beh of FSMctrl is
+	type states is(S0,S1,S2,S3,S4,S5,S6,S7);
+	signal EA, PE: states;
+	signal clock: std_logic;
+	signal reset: std_logic;
+	
+begin
+
+	clock <= CLK;
+	
+	P1: process(clock, reset)
+	begin
+		if reset = '0' then
+			EA <= S0;
+		elsif clock'event and clock = '1' then
+			EA <= PE;
+		end if;
+	end process;
+	
+	P2: process(EA, ENTER, Operacao)
+	begin
+		case EA is
+		
+			when S0 =>
+				if Enter = '1' then
+					PE <= S0;
+				else
+					PE <= S1;
+				end if;
+				Enable_1 <= '0';
+				Enable_2 <= '0';
+				
+			when S1 =>
+				if Enter = '0' then
+					PE <= S1;
+				else
+					PE <= S2;
+				end if;
+				Enable_1 <= '1';
+				Enable_2 <= '0';
+			
+			when S2 =>
+				Enable_1 <= '0';
+				Enable_2 <= '0';
+				if Operacao = "00" then
+					PE <= S3;
+				elsif Operacao = "01" then
+					PE <= S4;
+				elsif Operacao = "10" then
+					PE <= S5;
+				elsif Operacao = "11" then
+					PE <= S6;
+				end if;
+				
+			when S3 =>
+				Selecao <= "00";
+				if Enter = '1' then
+					PE <= S3;
+				else
+					PE <= S7;
+				end if;
+				
+			when S4 =>
+				Selecao <= "01";
+				if Enter = '1' then
+					PE <= S4;
+				else
+					PE <= S7;
+				end if;
+			
+			when S5 =>
+				Selecao <= "10";
+				if Enter = '1' then
+					PE <= S5;
+				else
+					PE <= S7;
+				end if;
+			   
+			when S6 =>
+				Enable_1 <= '0';
+				Enable_2 <= '1';
+				Selecao <= "11";
+				PE <= S0;
+			
+			when S7 =>
+				Enable_1 <= '0';
+				Enable_2 <= '1';
+				PE <= S0; 
+			
+		end case;
+	end process;
+end FSM_beh;
+	
+	
+	
+