{"payload":{"header_redesign_enabled":false,"results":[{"id":"9062266","archived":false,"color":"#b2b7f8","followers":941,"has_funding_file":false,"hl_name":"EttusResearch/uhd","hl_trunc_description":"The USRP™ Hardware Driver Repository","language":"Verilog","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":9062266,"name":"uhd","owner_id":125709,"owner_login":"EttusResearch","updated_at":"2024-06-28T14:54:21.363Z","has_issues":true}},"sponsorable":false,"topics":["fpga","driver","sdr","usrp","uhd"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":89,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AEttusResearch%252Fuhd%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/EttusResearch/uhd/star":{"post":"3urU6BgsJEW691LDlMz37eTDMTkN88Jzgo0GtiLIk9y4V3yri8lo3_4KFTsfeJlqpXuUvkmcL4K-VXRzaMqXyw"},"/EttusResearch/uhd/unstar":{"post":"aFfchYn53gCr4JAdhTi3kb4dNos5yYX-rYhBfHEepLpqC7EbyWE-81QW3Gyoepq_V5bCJl2zeYtyK_aRWcLk7A"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"5d_xIFqvvdqbzKCaYJ1qjYi6bmvB-xYuqnL9jqCMogw-APbwYpbLz0Yy6j_hCHsBe3LSAuh29oVtq4_V4N-08Q"}}},"title":"Repository search results"}