diff --git a/src/project.v b/src/project.v
index 41bf38e..b40e2b2 100644
--- a/src/project.v
+++ b/src/project.v
@@ -37,12 +37,12 @@ module tt_um_Electom_cla_4bits(
     assign g = a & b;
     assign p = a | b;
   
-	  assign c[0] = g[0] | (p[0] & ci);
-	  assign c[1] = g[1] | (p[1] & g[0]) | (p[1] & p[0] & ci);
-	  assign c[2] = g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & ci);
-	  assign co_w = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]) | (p[3] & p[2] & p[1] & p[0] & ci);
+    assign c[0] = g[0] | (p[0] & ci);
+    assign c[1] = g[1] | (p[1] & g[0]) | (p[1] & p[0] & ci);
+    assign c[2] = g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & ci);
+    assign co_w = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]) | (p[3] & p[2] & p[1] & p[0] & ci);
   
-	  assign s_w = (p & ~g) ^ {c[2 : 0], ci};
+    assign s_w = (p & ~g) ^ {c[2 : 0], ci};
 
     always @(posedge clk or negedge rst_n) begin
         if(!rst_n) begin