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Not really an issue, more an interested inquiry as I am also using ATSAME51 and ATSAMC21 for quite some time now.
I have not checked the software, if there is any to take a peek at, I just came across this repository.
Are you really ok with the TSX-3225 25.0000MF10P and the 22pF capacitors for it when running CAN-FD?
First of all this crystal has a load capacitance of 18pF and using the "Load Capacitance Equation" in the SAM E51 family datasheet, using 27pF would be a bit more apropriate.
This is only a minor deviation, but does the CAN-FD really work with up to 8MBit/s with this while sending out 64 byte packages?
And on a first glance I found the 25MHz odd for the crystal as I usually go with 16MHz and I know that the PLL has a maximum
input frequency of 3.2MHz.
But well, setting DPLLCTRLB.DIV to 4 gives a clock divider of 10 and so a multiplier of 48 to get to 120MHz can be used.
And a multplier of 32 on the second PLL for the CAN module to be clocked at 80Mhz or perhaps 40 to use the maximum input clock of 100MHz for the CAN, ADC and SERCOM modules.
The text was updated successfully, but these errors were encountered:
Not really an issue, more an interested inquiry as I am also using ATSAME51 and ATSAMC21 for quite some time now.
I have not checked the software, if there is any to take a peek at, I just came across this repository.
Are you really ok with the TSX-3225 25.0000MF10P and the 22pF capacitors for it when running CAN-FD?
First of all this crystal has a load capacitance of 18pF and using the "Load Capacitance Equation" in the SAM E51 family datasheet, using 27pF would be a bit more apropriate.
This is only a minor deviation, but does the CAN-FD really work with up to 8MBit/s with this while sending out 64 byte packages?
And on a first glance I found the 25MHz odd for the crystal as I usually go with 16MHz and I know that the PLL has a maximum
input frequency of 3.2MHz.
But well, setting DPLLCTRLB.DIV to 4 gives a clock divider of 10 and so a multiplier of 48 to get to 120MHz can be used.
And a multplier of 32 on the second PLL for the CAN module to be clocked at 80Mhz or perhaps 40 to use the maximum input clock of 100MHz for the CAN, ADC and SERCOM modules.
The text was updated successfully, but these errors were encountered: