add extension keyword to GCC statement expressions

Add __extension__ keyword to gcc statement expression extensions.
This is necessary for MSVC support.

Signed-off-by: Tyler Retzlaff <[email protected]>
Reviewed-by: Ruifeng Wang <[email protected]>

Author: Tyler Retzlaff

drivers/bus/fslmc/mc/fsl_mc_sys.h

@@ -40,11 +40,11 @@ struct fsl_mc_io {
 #define __arch_putq(v, a)	(*(volatile uint64_t *)(a) = (v))
 #define __arch_putq32(v, a)	(*(volatile uint32_t *)(a) = (v))
 #define readq(c) \
-	({ uint64_t __v = __arch_getq(c); __iormb(); __v; })
+	__extension__ ({ uint64_t __v = __arch_getq(c); __iormb(); __v; })
 #define writeq(v, c) \
-	({ uint64_t __v = v; __iowmb(); __arch_putq(__v, c); __v; })
+	__extension__ ({ uint64_t __v = v; __iowmb(); __arch_putq(__v, c); __v; })
 #define writeq32(v, c) \
-	({ uint32_t __v = v; __iowmb(); __arch_putq32(__v, c); __v; })
+	__extension__ ({ uint32_t __v = v; __iowmb(); __arch_putq32(__v, c); __v; })
 #define ioread64(_p)		readq(_p)
 #define iowrite64(_v, _p)	writeq(_v, _p)
 #define iowrite32(_v, _p)	writeq32(_v, _p)

drivers/common/cnxk/roc_io.h

@@ -30,21 +30,21 @@
 #endif
 
 #define roc_load_pair(val0, val1, addr)                                        \
-	({                                                                     \
+	__extension__ ({                                                                     \
 		asm volatile("ldp %x[x0], %x[x1], [%x[p1]]"                    \
 			     : [x0] "=r"(val0), [x1] "=r"(val1)                \
 			     : [p1] "r"(addr));                                \
 	})
 
 #define roc_store_pair(val0, val1, addr)                                       \
-	({                                                                     \
+	__extension__ ({                                                                     \
 		asm volatile(                                                  \
 			"stp %x[x0], %x[x1], [%x[p1], #0]!" ::[x0] "r"(val0),  \
 			[x1] "r"(val1), [p1] "r"(addr));                       \
 	})
 
 #define roc_prefetch_store_keep(ptr)                                           \
-	({ asm volatile("prfm pstl1keep, [%x0]\n" : : "r"(ptr)); })
+	__extension__ ({ asm volatile("prfm pstl1keep, [%x0]\n" : : "r"(ptr)); })
 
 #if defined(__clang__)
 static __plt_always_inline void

drivers/common/cnxk/roc_platform.h

@@ -82,7 +82,7 @@
 
 /** Divide ceil */
 #define PLT_DIV_CEIL(x, y)			\
-	({					\
+	__extension__ ({			\
 		__typeof(x) __x = x;		\
 		__typeof(y) __y = y;		\
 		(__x + __y - 1) / __y;		\

drivers/common/dpaax/dpaa_list.h

@@ -31,7 +31,7 @@ do { \
 #define list_entry(node, type, member) \
 	(type *)((void *)node - offsetof(type, member))
 #define list_empty(p) \
-({ \
+__extension__ ({ \
 	const struct list_head *__p298 = (p); \
 	((__p298->next == __p298) && (__p298->prev == __p298)); \
 })

drivers/common/qat/qat_adf/icp_qat_hw.h

@@ -292,7 +292,7 @@ enum icp_qat_hw_cipher_convert {
 #define QAT_CIPHER_AEAD_AAD_SIZE_BITPOS 16
 #define QAT_CIPHER_AEAD_AAD_SIZE_LE_BITPOS 0
 #define ICP_QAT_HW_CIPHER_CONFIG_BUILD_UPPER(aad_size) \
-	({ \
+	__extension__ ({ \
 	typeof(aad_size) aad_size1 = aad_size; \
 	(((((aad_size1) >> QAT_CIPHER_AEAD_AAD_UPPER_SHIFT) & \
 	QAT_CIPHER_AEAD_AAD_SIZE_UPPER_MASK) << \

drivers/crypto/armv8/rte_armv8_pmd.c

@@ -139,7 +139,7 @@ crypto_chain_order[] = {
  * Extract particular combined mode crypto function from the 3D array.
  */
 #define CRYPTO_GET_ALGO(order, cop, calg, aalg, keyl)			\
-({									\
+__extension__ ({							\
 	crypto_func_tbl_t *func_tbl =					\
 				(crypto_chain_order[(order)])[(cop)];	\
 									\
@@ -186,7 +186,7 @@ crypto_key_sched_dir[] = {
  * Extract particular combined mode crypto function from the 3D array.
  */
 #define CRYPTO_GET_KEY_SCHED(cop, calg, keyl)				\
-({									\
+__extension__ ({							\
 	crypto_key_sched_tbl_t *ks_tbl = crypto_key_sched_dir[(cop)];	\
 									\
 	(calg >= CRYPTO_CIPHER_MAX) ?					\

drivers/crypto/caam_jr/caam_jr_desc.h

@@ -32,7 +32,7 @@
 /* Macro for setting up a JD. The structure of the JD is common across all
  * supported protocols, thus its structure is identical.
  */
-#define SEC_JD_INIT(descriptor)	      ({ \
+#define SEC_JD_INIT(descriptor)	      __extension__ ({ \
 	/* CTYPE = job descriptor			       \
 	 * RSMS, DNR = 0
 	 * ONE = 1

drivers/dma/hisilicon/hisi_dmadev.c

@@ -124,7 +124,7 @@ hisi_dma_update_queue_mbit(struct hisi_dma_dev *hw, uint32_t qoff,
 	hisi_dma_write_queue(hw, qoff, tmp);
 }
 
-#define hisi_dma_poll_hw_state(hw, val, cond, sleep_us, timeout_us) ({ \
+#define hisi_dma_poll_hw_state(hw, val, cond, sleep_us, timeout_us) __extension__ ({ \
 	uint32_t timeout = 0; \
 	while (timeout++ <= (timeout_us)) { \
 		(val) = hisi_dma_read_queue(hw, HISI_DMA_QUEUE_FSM_REG); \

drivers/event/octeontx/ssovf_evdev.h

@@ -96,14 +96,14 @@
 
 /* ARM64 specific functions */
 #if defined(RTE_ARCH_ARM64)
-#define ssovf_load_pair(val0, val1, addr) ({		\
+#define ssovf_load_pair(val0, val1, addr) __extension__ ({		\
 			asm volatile(			\
 			"ldp %x[x0], %x[x1], [%x[p1]]"	\
 			:[x0]"=r"(val0), [x1]"=r"(val1) \
 			:[p1]"r"(addr)			\
 			); })
 
-#define ssovf_store_pair(val0, val1, addr) ({		\
+#define ssovf_store_pair(val0, val1, addr) __extension__ ({		\
 			asm volatile(			\
 			"stp %x[x0], %x[x1], [%x[p1]]"	\
 			::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \

drivers/mempool/octeontx/octeontx_fpavf.h

@@ -59,14 +59,14 @@
 
 /* ARM64 specific functions */
 #if defined(RTE_ARCH_ARM64)
-#define fpavf_load_pair(val0, val1, addr) ({		\
+#define fpavf_load_pair(val0, val1, addr) __extension__ ({		\
 			asm volatile(			\
 			"ldp %x[x0], %x[x1], [%x[p1]]"	\
 			:[x0]"=r"(val0), [x1]"=r"(val1) \
 			:[p1]"r"(addr)			\
 			); })
 
-#define fpavf_store_pair(val0, val1, addr) ({		\
+#define fpavf_store_pair(val0, val1, addr) __extension__ ({		\
 			asm volatile(			\
 			"stp %x[x0], %x[x1], [%x[p1]]"	\
 			::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \