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cpcec.c
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cpcec.c
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// #### ###### #### ####### #### ----------------------- //
// ## ## ## ## ## ## ## # ## ## CPCEC, plain text Amstrad //
// ## ## ## ## ## # ## CPC emulator written in C //
// ## ##### ## #### ## as a postgraduate project //
// ## ## ## ## # ## by Cesar Nicolas-Gonzalez //
// ## ## ## ## ## ## # ## ## since 2018-12-01 till now //
// #### #### #### ####### #### ----------------------- //
#define MY_CAPTION "CPCEC"
#define my_caption "cpcec"
#define MY_VERSION "20210930"//"2555"
#define MY_LICENSE "Copyright (C) 2019-2021 Cesar Nicolas-Gonzalez"
/* This notice applies to the source code of CPCEC and its binaries.
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Contact information: <mailto:[email protected]> */
// The emulation of the Amstrad CPC family is complex because the
// multiple devices are tightly knit together; it's no surprise that
// late models merged most (if not all) devices into a single custom
// ASIC chip to cut costs down without losing any relevant function.
// This file provides CPC-specific features for configuration, Gate
// Array and CRTC, Z80 timings and support, and snapshot handling.
#include <stdio.h> // printf()...
#include <stdlib.h> // strtol()...
#include <string.h> // strcpy()...
// Amstrad CPC metrics and constants defined as general types ------- //
#define MAIN_FRAMESKIP_BITS 4
#define VIDEO_PLAYBACK 50
#define VIDEO_LENGTH_X (64<<4)
#define VIDEO_LENGTH_Y (39<<4)
#define VIDEO_OFFSET_X (15<<4)
#define VIDEO_OFFSET_Y (17<<2) // (4<<4) //
#define VIDEO_PIXELS_X (48<<4)
#define VIDEO_PIXELS_Y (67<<3) // (34<<4) //
#define VIDEO_HSYNC_LO (62<<4)
#define VIDEO_HSYNC_HI (66<<4)
#define VIDEO_VSYNC_LO (37<<4)
#define VIDEO_VSYNC_HI (44<<4)
#define AUDIO_PLAYBACK 44100 // 22050, 24000, 44100, 48000
#define AUDIO_LENGTH_Z (AUDIO_PLAYBACK/VIDEO_PLAYBACK) // division must be exact!
#define DEBUG_LENGTH_X 64
#define DEBUG_LENGTH_Y 32
#define session_debug_show z80_debug_show
#define session_debug_user z80_debug_user
#if defined(SDL2)||!defined(_WIN32)
unsigned short session_icon32xx16[32*32] = {
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0X0000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000, 0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0X0000,
0XF000,0XF000,0XF000,0XFF00,0XFF00,0XFF00,0XFF00,0XFF00,0XFF00,0XF000,0XF000,0XF000,0XF000,0XF0F0,0XF0F0,0XF0F0, 0XF0F0,0XF0F0,0XF0F0,0XF000,0XF000,0XF000,0XF000,0XF08F,0XF08F,0XF08F,0XF08F,0XF08F,0XF08F,0XF000,0XF000,0XF000,
0XF000,0XF000,0XFF00,0XFF00,0XFF00,0XFF00,0XFF00,0XFF00,0XFF00,0XFF00,0XF000,0XF000,0XF0F0,0XF0F0,0XF0F0,0XF0F0, 0XF0F0,0XF0F0,0XF0F0,0XF0F0,0XF000,0XF000,0XF08F,0XF08F,0XF08F,0XF08F,0XF08F,0XF08F,0XF08F,0XF08F,0XF000,0XF000,
0XF000,0XF000,0XFF00,0XFF00,0XFFFF,0XFFFF,0XFFFF,0XFFFF,0XFF00,0XFF00,0XF000,0XF000,0XF0F0,0XF0F0,0XFFFF,0XFFFF, 0XFFFF,0XFFFF,0XF0F0,0XF0F0,0XF000,0XF000,0XF08F,0XF08F,0XFFFF,0XFFFF,0XFFFF,0XFFFF,0XF08F,0XF08F,0XF000,0XF000,
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0XF000,0XF000,0XFF00,0XFFFF,0XFFFF,0XFFFF,0XFFFF,0XFFFF,0XFFFF,0XFF00,0XF000,0XF000,0XF0F0,0XFFFF,0XFFFF,0XFFFF, 0XFFFF,0XFFFF,0XFFFF,0XF0F0,0XF000,0XF000,0XF08F,0XFFFF,0XFFFF,0XFFFF,0XFFFF,0XFFFF,0XFFFF,0XF08F,0XF000,0XF000,
0XF000,0XF000,0XFF00,0XFFFF,0XFFFF,0XFFFF,0XFFFF,0XFFFF,0XFFFF,0XFF00,0XF000,0XF000,0XF0F0,0XFFFF,0XFFFF,0XFFFF, 0XFFFF,0XFFFF,0XFFFF,0XF0F0,0XF000,0XF000,0XF08F,0XFFFF,0XFFFF,0XFFFF,0XFFFF,0XFFFF,0XFFFF,0XF08F,0XF000,0XF000,
0XF000,0XF000,0XFF00,0XFF00,0XFFFF,0XFFFF,0XFFFF,0XFFFF,0XFF00,0XFF00,0XF000,0XF000,0XF0F0,0XF0F0,0XFFFF,0XFFFF, 0XFFFF,0XFFFF,0XF0F0,0XF0F0,0XF000,0XF000,0XF08F,0XF08F,0XFFFF,0XFFFF,0XFFFF,0XFFFF,0XF08F,0XF08F,0XF000,0XF000,
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0XF000,0XF000,0XFF00,0XFF00,0XFF00,0XFF00,0XFF00,0XFF00,0XFF00,0XFF00,0XF000,0XF000,0XF0F0,0XF0F0,0XF0F0,0XF0F0, 0XF0F0,0XF0F0,0XF0F0,0XF0F0,0XF000,0XF000,0XF08F,0XF08F,0XF08F,0XF08F,0XF08F,0XF08F,0XF08F,0XF08F,0XF000,0XF000,
0XF000,0XF000,0XFF00,0XFF00,0XFF00,0XFF00,0XFF00,0XFF00,0XFF00,0XFF00,0XF000,0XF000,0XF0F0,0XF0F0,0XF0F0,0XF0F0, 0XF0F0,0XF0F0,0XF0F0,0XF0F0,0XF000,0XF000,0XF08F,0XF08F,0XF08F,0XF08F,0XF08F,0XF08F,0XF08F,0XF08F,0XF000,0XF000,
0XF000,0XF000,0XF800,0XFF00,0XFF00,0XFF00,0XFF00,0XFF00,0XFF00,0XF800,0XF000,0XF000,0XF080,0XF0F0,0XF0F0,0XF0F0, 0XF0F0,0XF0F0,0XF0F0,0XF080,0XF000,0XF000,0XF048,0XF08F,0XF08F,0XF08F,0XF08F,0XF08F,0XF08F,0XF048,0XF000,0XF000,
0XF000,0XF000,0XF800,0XF800,0XF800,0XF800,0XF800,0XF800,0XF800,0XF800,0XF000,0XF000,0XF080,0XF080,0XF080,0XF080, 0XF080,0XF080,0XF080,0XF080,0XF000,0XF000,0XF048,0XF048,0XF048,0XF048,0XF048,0XF048,0XF048,0XF048,0XF000,0XF000,
0XF000,0XF000,0XF800,0XF800,0XF800,0XF800,0XF800,0XF800,0XF800,0XF800,0XF000,0XF000,0XF080,0XF080,0XF080,0XF080, 0XF080,0XF080,0XF080,0XF080,0XF000,0XF000,0XF048,0XF048,0XF048,0XF048,0XF048,0XF048,0XF048,0XF048,0XF000,0XF000,
0XF000,0XF000,0XF800,0XF800,0XF800,0XF800,0XF800,0XF800,0XF800,0XF800,0XF000,0XF000,0XF080,0XF080,0XF080,0XF080, 0XF080,0XF080,0XF080,0XF080,0XF000,0XF000,0XF048,0XF048,0XF048,0XF048,0XF048,0XF048,0XF048,0XF048,0XF000,0XF000,
0XF000,0XF000,0XF800,0XF800,0XF800,0XF800,0XF800,0XF800,0XF800,0XF800,0XF000,0XF000,0XF080,0XF080,0XF080,0XF080, 0XF080,0XF080,0XF080,0XF080,0XF000,0XF000,0XF048,0XF048,0XF048,0XF048,0XF048,0XF048,0XF048,0XF048,0XF000,0XF000,
0XF000,0XF000,0XF800,0XF800,0XF800,0XF800,0XF800,0XF800,0XF800,0XF800,0XF000,0XF000,0XF080,0XF080,0XF080,0XF080, 0XF080,0XF080,0XF080,0XF080,0XF000,0XF000,0XF048,0XF048,0XF048,0XF048,0XF048,0XF048,0XF048,0XF048,0XF000,0XF000,
0XF000,0XF000,0XF000,0XF800,0XF800,0XF800,0XF800,0XF800,0XF800,0XF000,0XF000,0XF000,0XF000,0XF080,0XF080,0XF080, 0XF080,0XF080,0XF080,0XF000,0XF000,0XF000,0XF000,0XF048,0XF048,0XF048,0XF048,0XF048,0XF048,0XF000,0XF000,0XF000,
0X0000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000, 0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0X0000,
0X0000,0X0000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000, 0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0XF000,0X0000,0X0000,
};
#endif
// The CPC 6128 and PLUS keyboard; older models had the cursors (00,02,08,01) and COPY (09) on the right edge.
// +-----------------------------------------------------------------------------------------+ +----+
// | 42 | 40 | 41 | 39 | 38 | 31 | 30 | 29 | 28 | 21 | 20 | 19 | 18 | 10 | 4F | 0A | 0B | 03 | | 48 |
// +-----------------------------------------------------------------------------------------+ +----+----+----+
// | 44 | 43 | 3B | 3A | 32 | 33 | 2B | 2A | 23 | 22 | 1B | 1A | 11 | | 14 | 0C | 04 | | 4A | // | 4B |
// +--------------------------------------------------------------------+ 12 +--------------+ +----+----+----+
// | 46 | 45 | 3C | 3D | 35 | 34 | 2C | 2D | 25 | 24 | 1D | 1C | 13 | | 0D | 0E | 05 | | 49 |
// +-----------------------------------------------------------------------------------------+ +----+
// | 15 | 47 | 3F | 3E | 37 | 36 | 2E | 26 | 27 | 1F | 1E | 16 | 15 | 0F | 00 | 07 | Amstrad joystick
// +-----------------------------------------------------------------------------------------+ +--------------+
// | 17 | 09 | 2F | 06 | 08 | 02 | 01 | | 4C | 4D | 4E |
// +-----------------------------------------------------------------------------------------+ +--------------+
#define KBD_JOY_UNIQUE 6 // exclude repeated buttons
unsigned char kbd_joy[]= // ATARI norm: up, down, left, right, fire1-fire4
{ 0X48,0X49,0X4A,0X4B,0X4C,0X4D,0X4C,0X4D }; // constant, joystick bits are hard-wired; last two fires are repeated
#define MAUS_EMULATION // emulation can examine the mouse
#define MAUS_LIGHTGUNS // lightguns are emulated with the mouse
#include "cpcec-os.h" // OS-specific code!
#include "cpcec-rt.h" // OS-independent code!
int litegun=0; // 0 = standard joystick, 1 = Trojan Light Phaser, 2 = Gunstick (MHT), 3 = Westphaser (Loriciel)
const unsigned char kbd_map_xlt[]=
{
// control keys
KBCODE_F1 ,0x81, KBCODE_F2 ,0x82, KBCODE_F3 ,0x83, KBCODE_F4 ,0x84,
KBCODE_F5 ,0x85, KBCODE_F6 ,0x86, KBCODE_F7 ,0x87, KBCODE_F8 ,0x88,
KBCODE_F9 ,0x89, KBCODE_HOLD ,0x8F, KBCODE_F11 ,0x8B, KBCODE_F12 ,0x8C,
KBCODE_X_ADD ,0x91, KBCODE_X_SUB ,0x92, KBCODE_X_MUL ,0x93, KBCODE_X_DIV ,0x94,
#ifdef DEBUG
KBCODE_PRIOR ,0x95, KBCODE_NEXT ,0x96, KBCODE_HOME ,0x97, KBCODE_END ,0x98,
#endif
// actual keys
KBCODE_1 ,0x40, KBCODE_Q ,0x43, KBCODE_A ,0x45, KBCODE_Z ,0x47,
KBCODE_2 ,0x41, KBCODE_W ,0x3B, KBCODE_S ,0x3C, KBCODE_X ,0x3F,
KBCODE_3 ,0x39, KBCODE_E ,0x3A, KBCODE_D ,0x3D, KBCODE_C ,0x3E,
KBCODE_4 ,0x38, KBCODE_R ,0x32, KBCODE_F ,0x35, KBCODE_V ,0x37,
KBCODE_5 ,0x31, KBCODE_T ,0x33, KBCODE_G ,0x34, KBCODE_B ,0x36,
KBCODE_6 ,0x30, KBCODE_Y ,0x2B, KBCODE_H ,0x2C, KBCODE_N ,0x2E,
KBCODE_7 ,0x29, KBCODE_U ,0x2A, KBCODE_J ,0x2D, KBCODE_M ,0x26,
KBCODE_8 ,0x28, KBCODE_I ,0x23, KBCODE_K ,0x25, KBCODE_CHR4_1 ,0x27,
KBCODE_9 ,0x21, KBCODE_O ,0x22, KBCODE_L ,0x24, KBCODE_CHR4_2 ,0x1F,
KBCODE_0 ,0x20, KBCODE_P ,0x1B, KBCODE_CHR3_1 ,0x1D, KBCODE_CHR4_3 ,0x1E,
KBCODE_CHR1_1 ,0x19, KBCODE_CHR2_1 ,0x1A, KBCODE_CHR3_2 ,0x1C, KBCODE_CHR4_4 ,0x16,
KBCODE_CHR1_2 ,0x18, KBCODE_CHR2_2 ,0x11, KBCODE_CHR3_3 ,0x13,
KBCODE_TAB ,0x44, KBCODE_CAPSLOCK ,0x46, KBCODE_L_SHIFT ,0x15, KBCODE_L_CTRL ,0x17,
KBCODE_ESCAPE ,0x42, KBCODE_BKSPACE ,0x4F, KBCODE_ENTER ,0x12, KBCODE_SPACE ,0x2F,
KBCODE_X_7 ,0x0A, KBCODE_X_8 ,0x0B, KBCODE_X_9 ,0x03, KBCODE_DELETE ,0x10,
KBCODE_X_4 ,0x14, KBCODE_X_5 ,0x0C, KBCODE_X_6 ,0x04, KBCODE_INSERT ,0x09,
KBCODE_X_1 ,0x0D, KBCODE_X_2 ,0x0E, KBCODE_X_3 ,0x05,
KBCODE_X_0 ,0x0F, KBCODE_X_DOT ,0x07, KBCODE_X_ENTER ,0x06,
KBCODE_UP ,0x00, KBCODE_DOWN ,0x02, KBCODE_LEFT ,0x08, KBCODE_RIGHT ,0x01,
// key mirrors
KBCODE_R_SHIFT ,0x15, KBCODE_R_CTRL ,0x17, KBCODE_CHR4_5 ,0x16,
};
const int video_asic_table[32]= // the 0GRB format used in ASIC PLUS
{
0X666,0X666,0XF06,0XFF6,0X006,0X0F6,0X606,0X6F6, // "6" ensures that PREHISTORIK 2 PLUS shows well the scores
0X0F6,0XFF6,0XFF0,0XFFF,0X0F0,0X0FF,0X6F0,0X6FF,
0X006,0XF06,0XF00,0XF0F,0X000,0X00F,0X600,0X60F,
0X066,0XF66,0XF60,0XF6F,0X060,0X06F,0X660,0X66F,
};
const VIDEO_UNIT video_table[][80]= // colour table, 0xRRGGBB style: the 32 original colours, followed by 16 levels of G, 16 of R and 16 of B
{
// monochrome - black and white
{
0X808080,0X808080,0XBABABA,0XF5F5F5,
0X0A0A0A,0X454545,0X626262,0X9D9D9D,
0X454545,0XF5F5F5,0XEBEBEB,0XFFFFFF,
0X3B3B3B,0X4E4E4E,0X939393,0XA7A7A7,
0X0A0A0A,0XBABABA,0XB0B0B0,0XC4C4C4,
0X000000,0X141414,0X595959,0X6C6C6C,
0X272727,0XD8D8D8,0XCECECE,0XE2E2E2,
0X1D1D1D,0X313131,0X767676,0X8A8A8A,
// OLD -/- NEW //
0X000000,0X0C0C0C,0X171717,0X232323,
0X2F2F2F,0X3B3B3B,0X474747,0X525252,
0X5E5E5E,0X6A6A6A,0X767676,0X818181,
0X8D8D8D,0X999999,0XA5A5A5,0XB0B0B0,
0X000000,0X040404,0X080808,0X0C0C0C,
0X101010,0X141414,0X171717,0X1B1B1B,
0X1F1F1F,0X232323,0X272727,0X2B2B2B,
0X2F2F2F,0X333333,0X373737,0X3B3B3B,
0X000000,0X010101,0X030303,0X040404,
0X050505,0X060606,0X080808,0X090909,
0X0A0A0A,0X0C0C0C,0X0D0D0D,0X0E0E0E,
0X101010,0X111111,0X121212,0X141414,
},
// dark colour
{
0X555555,0X555555,0X00FF55,0XFFFF55,
0X000055,0XFF0055,0X005555,0XFF5555,
0XFF0055,0XFFFF55,0XFFFF00,0XFFFFFF,
0XFF0000,0XFF00FF,0XFF5500,0XFF55FF,
0X000055,0X00FF55,0X00FF00,0X00FFFF,
0X000000,0X0000FF,0X005500,0X0055FF,
0X550055,0X55FF55,0X55FF00,0X55FFFF,
0X550000,0X5500FF,0X555500,0X5555FF,
// OLD -/- NEW //
0X000000,0X000100,0X000600,0X000C00,
0X001600,0X002200,0X003100,0X004100,
0X005400,0X006900,0X007F00,0X009700,
0X00B000,0X00CA00,0X00E400,0X00FF00,
0X000000,0X010000,0X060000,0X0C0000,
0X160000,0X220000,0X310000,0X410000,
0X540000,0X690000,0X7F0000,0X970000,
0XB00000,0XCA0000,0XE40000,0XFF0000,
0X000000,0X000001,0X000006,0X00000C,
0X000016,0X000022,0X000031,0X000041,
0X000054,0X000069,0X00007F,0X000097,
0X0000B0,0X0000CA,0X0000E4,0X0000FF,
},
// normal colour
{
0X808080,0X808080,0X00FF80,0XFFFF80,
0X000080,0XFF0080,0X008080,0XFF8080,
0XFF0080,0XFFFF80,0XFFFF00,0XFFFFFF,
0XFF0000,0XFF00FF,0XFF8000,0XFF80FF,
0X000080,0X00FF80,0X00FF00,0X00FFFF,
0X000000,0X0000FF,0X008000,0X0080FF,
0X800080,0X80FF80,0X80FF00,0X80FFFF,
0X800000,0X8000FF,0X808000,0X8080FF,
// OLD -/- NEW //
0X000000,0X001100,0X002200,0X003300,
0X004400,0X005500,0X006600,0X007700,
0X008800,0X009900,0X00AA00,0X00BB00,
0X00CC00,0X00DD00,0X00EE00,0X00FF00,
0X000000,0X110000,0X220000,0X330000,
0X440000,0X550000,0X660000,0X770000,
0X880000,0X990000,0XAA0000,0XBB0000,
0XCC0000,0XDD0000,0XEE0000,0XFF0000,
0X000000,0X000011,0X000022,0X000033,
0X000044,0X000055,0X000066,0X000077,
0X000088,0X000099,0X0000AA,0X0000BB,
0X0000CC,0X0000DD,0X0000EE,0X0000FF,
},
// bright colour
{
0XAAAAAA,0XAAAAAA,0X00FFAA,0XFFFFAA,
0X0000AA,0XFF00AA,0X00AAAA,0XFFAAAA,
0XFF00AA,0XFFFFAA,0XFFFF00,0XFFFFFF,
0XFF0000,0XFF00FF,0XFFAA00,0XFFAAFF,
0X0000AA,0X00FFAA,0X00FF00,0X00FFFF,
0X000000,0X0000FF,0X00AA00,0X00AAFF,
0XAA00AA,0XAAFFAA,0XAAFF00,0XAAFFFF,
0XAA0000,0XAA00FF,0XAAAA00,0XAAAAFF,
// OLD -/- NEW //
0X000000,0X001B00,0X003500,0X004F00,
0X006800,0X007F00,0X009600,0X00AB00,
0X00BE00,0X00CE00,0X00DD00,0X00E900,
0X00F300,0X00F900,0X00FE00,0X00FF00,
0X000000,0X1B0000,0X350000,0X4F0000,
0X680000,0X7F0000,0X960000,0XAB0000,
0XBE0000,0XCE0000,0XDD0000,0XE90000,
0XF30000,0XF90000,0XFE0000,0XFF0000,
0X000000,0X00001B,0X000035,0X00004F,
0X000068,0X00007F,0X000096,0X0000AB,
0X0000BE,0X0000CE,0X0000DD,0X0000E9,
0X0000F3,0X0000F9,0X0000FE,0X0000FF,
},
// monochrome - green screen
{
0X45A445,0X45A445,0X5FCB5F,0X7DF87D,
0X054405,0X237123,0X358C35,0X53B953,
0X237123,0X7DF87D,0X78F078,0X82FF82,
0X1E691E,0X287828,0X4EB14E,0X58C058,
0X054405,0X5FCB5F,0X5AC35A,0X64D264,
0X003C00,0X0A4B0A,0X308430,0X3A933A,
0X155C15,0X6FE36F,0X6ADB6A,0X74EA74,
0X105410,0X1A631A,0X409C40,0X4AAB4A,
// OLD -/- NEW //
0X003C00,0X064506,0X0C4E0C,0X125712,
0X186018,0X1E691E,0X247224,0X2A7B2A,
0X308430,0X368D36,0X3C963C,0X429F42,
0X48A848,0X4EB14E,0X54BA54,0X5AC35A,
0X000000,0X020302,0X040604,0X060906,
0X080C08,0X0A0F0A,0X0C120C,0X0E150E,
0X101810,0X121B12,0X141E14,0X162116,
0X182418,0X1A271A,0X1C2A1C,0X1E2D1E,
0X000000,0X000100,0X010201,0X020302,
0X020402,0X030503,0X040604,0X040704,
0X050805,0X060906,0X060A06,0X070B07,
0X080C08,0X080D08,0X090E09,0X0A0F0A,
},
};
// sound table, 16 static levels + 1 dynamic level, 16-bit sample style
int audio_table[17]={0,85,121,171,241,341,483,683,965,1365,1931,2731,3862,5461,7723,10922,0};
// GLOBAL DEFINITIONS =============================================== //
#define TICKS_PER_FRAME ((VIDEO_LENGTH_X*VIDEO_LENGTH_Y)/32)
#define TICKS_PER_SECOND (TICKS_PER_FRAME*VIDEO_PLAYBACK)
// everything in the Amstrad CPC is tuned to a 4 MHz clock,
// using simple binary divisors to adjust the devices' timings,
// mainly defined by the simultaneous operation of the video output
// (32 horizontal thin pixels) and the Z80 behavior (4 cycles)
// (the clock is technically 16 MHz but we mean atomic steps here)
DWORD main_t=0; // the global tick counter, used by the debugger
int multi_t=1; // overclocking factor
// HARDWARE DEFINITIONS ============================================= //
BYTE mem_ram[9<<16],mem_rom[33<<14]; // RAM (BASE 64K BANK + 8x 64K BANKS) and ROM (512K ASIC PLUS CARTRIDGE + 16K BDOS)
BYTE *mem_xtr=NULL; // external 257x 16K EXTENDED ROMS
#define plus_enabled (type_id>2) // the PLUS ASIC hardware MUST BE tied to the model!
#define bdos_rom (&mem_rom[32<<14])
BYTE *mmu_ram[4],*mmu_rom[4]; // memory is divided in 14 6k R+W areas
BYTE mmu_bit[4]={0,0,0,0}; // RAM bit masks: nonzero raises a write event
BYTE mmu_xtr[257]; // ROM bit masks: nonzero reads from EXTENDED rather than from DEFAULT/CARTRIDGE
#define PEEK(x) mmu_rom[(x)>>14][x] // WARNING, x cannot be `x=EXPR`!
#define POKE(x) mmu_ram[(x)>>14][x] // WARNING, x cannot be `x=EXPR`!
BYTE type_id=2; // 0=464, 1=664, 2=6128, 3=PLUS
BYTE disc_disabled=0; // disables the disc drive altogether as well as its extended ROM
BYTE video_type=length(video_table)/2; // 0 = monochrome, 1=darkest colour, etc.
VIDEO_UNIT video_clut[32]; // precalculated colour palette, 16 bitmap inks, 1 border, 15 sprite inks
// Z80 registers: the hardware and the debugger must be allowed to "spy" on them!
Z80W z80_af,z80_bc,z80_de,z80_hl; // Accumulator+Flags, BC, DE, HL
Z80W z80_af2,z80_bc2,z80_de2,z80_hl2,z80_ix,z80_iy; // AF', BC', DE', HL', IX, IY
Z80W z80_pc,z80_sp,z80_iff,z80_ir; // Program Counter, Stack Pointer, Interrupt Flip-Flops, IR pair
BYTE z80_imd; // Interrupt Mode
BYTE z80_r7; // low 7 bits of R, required by several `IN X,(Y)` operations
// the Dandanator cartridge system can spy on the Z80 and trap its operations
#define Z80_CPC_DANDANATOR
BYTE *mem_dandanator=NULL; char dandanator_path[STRMAX]="";
WORD dandanator_trap,dandanator_temp; // Dandanator-Z80 watchdogs
BYTE dandanator_cfg[8]; // PENDING and CURRENT cnfg_0,cnfg_1,zone_0,zone_1 (A0,A1,B,C)
int dandanator_canwrite=0,dandanator_dirty; // R/W status
// above the Gate Array and the CRTC: PLUS ASIC --------------------- //
BYTE plus_gate_lock[]={0000,0x00,0xFF,0x77,0xB3,0x51,0xA8,0xD4,0x62,0x39,0x9C,0x46,0x2B,0x15,0x8A}; // dummy first byte
BYTE plus_gate_counter; // step in the plus lock sequence, starting from 0 (waiting for 0x00) until its length
BYTE plus_gate_enabled; // locked/unlocked state: UNLOCKED if byte after SEQUENCE is $CD, LOCKED otherwise!
BYTE plus_gate_mcr; // RMR2 register, that modifies the behavior of the original MRER (gate_mcr)
WORD plus_dma_regs[3][4]; // loop counter,loop address,pause counter,pause scaler
int plus_dma_index,plus_dma_delay,plus_dma_cache[3]; // DMA channel counters and timings
//BYTE plus_dirtysprite; // tag sprite as "dirty"
BYTE plus_8k_bug; // ASIC IRQ bug flag
// the following block is a hacky way to implement the entire Plus configuration RAM bank:
BYTE plus_bank[1<<14];
#define plus_sprite_bmp (plus_bank) // i.e. RAM address range 0x4000-0x4FFF
#define plus_sprite_xyz (&plus_bank[0x2000]) // i.e. range 0x6000-0x607F
#define plus_palette (&plus_bank[0x2400]) // i.e. range 0x6400-0x643F
#define plus_pri plus_bank[0x2800] // 0x6800: Programmable Raster Interrupt
#define plus_sssl plus_bank[0x2801] // 0x6801: Screen Split Scan Line
#define plus_ssss (&plus_bank[0x2802]) // 0x6802: Screen Split Secondary Start (CRTC order, High [0] and Low [1])
#define plus_sscr plus_bank[0x2804] // 0x6804: Soft Scroll Control Register
#define plus_ivr plus_bank[0x2805] // 0x6805: Interrupt Vector Register
#define plus_analog (&plus_bank[0x2808]) // 0x6808: analog joystick channels, effectively unused :-(
#define plus_dmas (&plus_bank[0x2C00]) // 0x6C00: DMA channels' pointers and prescalers (WORD address,BYTE scaler,BYTE dummy)
#define plus_dcsr plus_bank[0x2C0F] // 0x6C0F: DMA control/status register
//#define plus_icsr z80_irq // ICSR is more than one bit, but Z80_IRQ is true on nonzero, so they can overlap
#define plus_setup()
void plus_reset(void)
{
MEMZERO(plus_bank);
MEMZERO(plus_dma_regs);
plus_dma_index=plus_dma_delay=plus_gate_mcr=plus_gate_enabled=plus_gate_counter=0; // default configuration values
plus_analog[0]=plus_analog[1]=plus_analog[2]=plus_analog[3]=plus_analog[4]=plus_analog[6]=0x3F; // default analog values; WinAPE lets them stay ZERO
plus_ivr=1; // docs: "Interrupt Vector (Bit 0 set to 1 on reset)"; WinAPE uses 0x51 as the default state
plus_8k_bug=0; // the ASIC IRQ bug MUST happen once after reset at the very least ("CRTC3" demo)
}
BYTE gate_status; // low 2 bits are the current screen mode; next bits render either border or pure black
int video_threshold=VIDEO_LENGTH_X; // self-adjusting horizontal threshold, to gain speed when possible
int hsync_limit=VIDEO_LENGTH_X,hsync_count=0,hsync_match=0; // LA-7800: self-adjusting HSYNC timings
int vsync_limit=VIDEO_LENGTH_Y,vsync_count=0,vsync_match=0; // LA-7800: self-adjusting VSYNC timings
//int hsync_threshold,hsync_character; // configurable HSYNC thresholds
// 0xBC00-0xBF00: CRTC 6845 ----------------------------------------- //
const BYTE crtc_valid[18]={255,255,255,255,127,31,127,127,63,31,127,31,63,255,63,255,63,255}; // bit masks
BYTE crtc_index,crtc_table[18]; // index and table
BYTE crtc_type=1; // 0 Hitachi, 1 UMC, 2 Motorola, 3 Amstrad+, 4 Amstrad-
int crtc_status,crtc_before; // active status and latest events
// Winape `HDC` and `VDUR` are `video_pos_x` and `video_pos_y`
BYTE crtc_count_r0; // HORIZONTAL CHAR COUNT / Winape `HCC`
BYTE crtc_count_r4; // VERTICAL CHAR COUNT / Winape `VCC`
BYTE crtc_count_r9; // VERTICAL LINE COUNT / Winape `VLC`
BYTE crtc_count_r5; // V_T_A LINE COUNT / Winape `VTAC`
BYTE crtc_count_r3x; // HSYNC CHAR COUNT / Winape `HSC`
BYTE crtc_count_r3y; // VSYNC LINE COUNT / Winape `VSC`
BYTE crtc_limit_r3x,crtc_limit_r3y; // limits of `r3x` and `r3y`
int video_vsync_min,video_vsync_max,crtc_hold=0; // VHOLD modifiers
int crtc_line; // virtual PLUS variable, a shortcut of CRTC registers 4 and 9 used to test PLUS_PRI, PLUS_SSSL and others
#define crtc_line_set() (crtc_line=(crtc_count_r9&7)+(crtc_count_r4&63)*8) // Plus scanline counter
// these flags draw the border instead of the bitmap
#define CRTC_STATUS_H_OFF 4 // i.e. CRTC_STATUS_R1_OK
#define CRTC_STATUS_V_OFF 8 // i.e. CRTC_STATUS_R6_OK
#define CRTC_STATUS_INVIS 16 // different on CRTC1
// these flags draw pure black instead of bitmap and border
#define CRTC_STATUS_HSYNC 32 // i.e. CRTC_STATUS_R2_OK
#define CRTC_STATUS_VSYNC 64 // i.e. CRTC_STATUS_R7_OK
// the following flags are internal rather than visible
#define CRTC_STATUS_V_T_A 256 // i.e. Vertical Total Adjust
#define CRTC_STATUS_R0_OK 512
#define CRTC_STATUS_R4_OK 1024
#define CRTC_STATUS_R9_OK 2048
#define CRTC_STATUS_REG_8 128 // toggle to shake the screen
// CRTC_STATUS macros that SET and RESet bits and their associated counters
#define CRTC_STATUS_H_OFF_RES (crtc_status&=~CRTC_STATUS_H_OFF,crtc_count_r0=0)
#define CRTC_STATUS_H_OFF_SET (crtc_status|=CRTC_STATUS_H_OFF)
#define CRTC_STATUS_V_OFF_RES (crtc_status&=~CRTC_STATUS_V_OFF,crtc_count_r4=crtc_count_r9=0)
#define CRTC_STATUS_V_OFF_SET (crtc_status|=CRTC_STATUS_V_OFF)
#define CRTC_STATUS_HSYNC_SET (crtc_status|=CRTC_STATUS_HSYNC,crtc_count_r3x=0)
#define CRTC_STATUS_HSYNC_RES (crtc_status&=~CRTC_STATUS_HSYNC)
#define CRTC_STATUS_VSYNC_SET (crtc_status|=CRTC_STATUS_VSYNC,crtc_count_r3y=0)
#define CRTC_STATUS_VSYNC_RES (crtc_status&=~CRTC_STATUS_VSYNC)
void crtc_invis_update(void) // handle invisibility conditions
{
if (crtc_type!=1?~crtc_table[8]&48:crtc_table[6])
crtc_status&=~CRTC_STATUS_INVIS;
else
crtc_status|=CRTC_STATUS_INVIS;
}
void crtc_syncs_update(void) // horizontal and vertical limits
{
crtc_limit_r3x=crtc_table[3]&15; if (!crtc_limit_r3x&&crtc_type>=2) crtc_limit_r3x=16; // CRTC0,CRTC1: zero means NO HSYNC; CRTC2,CRTC3,CRTC4: zero means 16 CHARS
crtc_limit_r3y=(crtc_type<1||crtc_type>2)?crtc_table[3]>>4: // CRTC1,CRTC2: nibble is ignored, height is always 16 lines; CRTC0,CRTC3,CRTC4: zero means 16 LINES
crtc_table[4]==62&&crtc_table[9]==4&&!crtc_table[5]?15:0; // kludge: 15 (possibly 13 =16-(315-312)) rather than 0 can fix "PHEELONE" on CRTC1 (315 lines tall)
}
#define CRTC_STATUS_T_F(x) ((crtc_status&(x))?'*':'-')
INLINE void crtc_table_select(BYTE i) { crtc_index=i&16?i&17:i&15; } // i&17 satisfies "SKEETSHOT"; i&15 is required by "STILL RISING" (Pulpo Corrosivo part)
INLINE void crtc_table_send(BYTE i)
{
if (crtc_table[crtc_index]!=(i&=crtc_valid[crtc_index]))
switch (crtc_table[crtc_index]=i,crtc_index)
{
case 0:
if (!(crtc_type|i))
crtc_table[0]=i=1; // CRTC0: R0 CANNOT BE ZERO!
if (i==(crtc_table[7]?7:39)) // detect "CHANY DREAM END" and "CHAPELLE SIXTEEN" (but not "ONESCREEN COLONIES"); some of their effects are particularly time-critical
video_threshold=(VIDEO_LENGTH_X*5)>>3; // hard horizontal threshold
if (crtc_type<3?crtc_count_r0==i:crtc_count_r0>=i) // "S&KOH" intro needs the first check; "PHX" outro for CRTC3 and CRTC4 needs the second check
crtc_status|=CRTC_STATUS_R0_OK;
else
crtc_status&=~CRTC_STATUS_R0_OK;
break;
//case 1:
//if (crtc_count_r0==i) CRTC_STATUS_H_OFF_SET; // is this real? does any demo use it?
//break;
//case 2:
//if (crtc_count_r0==i) CRTC_STATUS_HSYNC_SET; // is this real? does any demo use it?
//break;
case 7:
if (crtc_count_r4==i&&crtc_type!=3) // "BYTE 98" (second half) must trigger a VSYNC, but "CROCO CHANEL 1 part 4" and "PHX" outro for CRTC3 must NOT!
CRTC_STATUS_VSYNC_SET;
break;
case 3:
crtc_syncs_update(); // split R3 into VSYNC and HSYNC limits
if (crtc_count_r0==crtc_table[2]) // "CHANY DREAM END part 8" (CRTC1 only) relies on this
CRTC_STATUS_HSYNC_SET;
break;
//case 5:
//cprintf("%04X:R5 %02X%c%02X ",z80_pc.w,i,CRTC_STATUS_T_F(CRTC_STATUS_V_T_A),crtc_count_r5); // can this do anything? does any demo use it?
//break;
case 6:
if (crtc_count_r4==i)
CRTC_STATUS_V_OFF_SET; // "VOYAGE 93" hides the bouncing staff with this!
// no `break`!
case 8:
crtc_invis_update(); // mix visibility of R6 and R8 together
break;
case 4:
if (crtc_type&5) // CRTC1, CRTC3 and CRTC4 are straightforward
{
if (crtc_type<3?crtc_count_r4==i:crtc_count_r4>=i) // no special cases, just 'EQUAL TO' for CRTC1 and 'GREATER THAN OR EQUAL TO' for CRTC3 and CRTC4
crtc_status|=CRTC_STATUS_R4_OK;
else
crtc_status&=~CRTC_STATUS_R4_OK;
}
else // CRTC0 and CRTC2 handle R4 and R9 together
{
if (crtc_status&CRTC_STATUS_R9_OK) // *!* todo: "DEMOIZART part 1" and "OVERFLOW PREVIEW part 2" need a more complex filter *!*
{
//if (crtc_count_r4==i)
//;//cprintf("%04X:R4 ",z80_pc.w); //crtc_status|=CRTC_STATUS_R4_OK; // setting R4_OK makes "PINBALL DREAMS" for CRTC1 run on CRTC0, but it should fail instead!
//else
//;//cprintf("%04X:r4 ",z80_pc.w); //crtc_status&=~CRTC_STATUS_R4_OK; // resetting R4_OK breaks the timings of "OVERFLOW PREVIEW part 1"
}
else // rejecting R9_OK is the bare minimum required by "STILL RISING", "ONESCREEN COLONIES" and other demos using CRTC0
if (crtc_count_r4==i)
crtc_status|=CRTC_STATUS_R4_OK;
else
crtc_status&=~CRTC_STATUS_R4_OK;
}
break;
case 9:
if (crtc_type&5) // CRTC1, CRTC3 and CRTC4 are straightforward
{
if (crtc_type<3?crtc_count_r9==i+(crtc_table[8]&1):crtc_count_r9>=i) // the only special case is the interlaced mode: "ECSTASY DEMO part 1" (CRTC1?)
crtc_status|=CRTC_STATUS_R9_OK;
else
crtc_status&=~CRTC_STATUS_R9_OK;
}
else // CRTC0 and CRTC2 handle R4 and R9 together
{
if (crtc_status&CRTC_STATUS_R4_OK) // *!* todo: "DEMOIZART part 1" and "OVERFLOW PREVIEW part 2" need a more complex filter *!*
{
if (crtc_count_r9==i)
crtc_status|=CRTC_STATUS_R9_OK; // setting R9_OK lets "POWER SYSTEM MEGADEMO (Glooms part)" for CRTC1 run on CRTC0 as expected.
//else
//;//cprintf("%04X:r9 ",z80_pc.w); //crtc_status&=~CRTC_STATUS_R9_OK; // resetting R9_OK corrupts the visuals of "OVERFLOW PREVIEW part 1"
}
else // rejecting R4_OK is the bare minimum required by "PRODATRON MEGADEMO part 4", "PINBALL DREAMS" (ingame) and others
if (crtc_count_r9==i)
crtc_status|=CRTC_STATUS_R9_OK;
else
crtc_status&=~CRTC_STATUS_R9_OK;
}
break;
}
}
BYTE crtc_table_recv(void)
{ return (crtc_index>=12&&crtc_index<18)?crtc_table[crtc_index]:(crtc_type>=3&&crtc_index<8?crtc_table[crtc_index+8]:0); }
INLINE BYTE crtc_table_info(void) { return crtc_count_r4>=crtc_table[6]?32:0; } // +64???
#define crtc_setup()
void crtc_reset(void)
{
MEMZERO(crtc_table);
crtc_before=crtc_status=0;//CRTC_STATUS_VSYNC+CRTC_STATUS_HSYNC+CRTC_STATUS_R9_OK+CRTC_STATUS_R4_OK;
crtc_index=crtc_count_r0=crtc_count_r4=crtc_count_r9=crtc_count_r5=crtc_count_r3x=crtc_count_r3y=0;
crtc_table[0]=63; crtc_table[3]=0x8E; crtc_table[4]=38; crtc_table[9]=7; // implicit in "GNG11B" (?)
crtc_syncs_update(),crtc_invis_update();
}
// 0x7F00, 0xDF00: Gate Array --------------------------------------- //
BYTE gate_index,gate_table[17]; // colour table: respectively, Palette Pointer Register and Palette Memory
BYTE gate_mcr; // bit depth + MMU configuration (1/3), also known as MRER (Mode and Rom Enable Register)
BYTE gate_ram; // MMU configuration (2/3), the Memory Mapping Register
BYTE gate_rom; // MMU configuration (3/3)
BYTE gate_ram_depth=1; // RAM configuration: 0 = 64k, 1 = 128k, 2 = 192k, 3 = 320k, 4 = 576k
int gate_ram_dirty; // actually used RAM space, in kb
int gate_ram_kbyte[]={64,128,192,320,576};// (x?(32<<x)+64:64)
VIDEO_UNIT *video_clut_index,video_clut_value; // slow colour update buffer
const int mmu_ram_mode[8][4]= // relative offsets of every bank for each +128K RAM mode
{
{ 0x00000-0x0000,0x04000-0x4000,0x08000-0x8000,0x0C000-0xC000 }, // RAM0: 0 1 2 3
{ 0x00000-0x0000,0x04000-0x4000,0x08000-0x8000,0x1C000-0xC000 }, // RAM1: 0 1 2 7
{ 0x10000-0x0000,0x14000-0x4000,0x18000-0x8000,0x1C000-0xC000 }, // RAM2: 4 5 6 7
{ 0x00000-0x0000,0x0C000-0x4000,0x08000-0x8000,0x1C000-0xC000 }, // RAM3: 0 3 2 7
{ 0x00000-0x0000,0x10000-0x4000,0x08000-0x8000,0x0C000-0xC000 }, // RAM4: 0 4 2 3
{ 0x00000-0x0000,0x14000-0x4000,0x08000-0x8000,0x0C000-0xC000 }, // RAM5: 0 5 2 3
{ 0x00000-0x0000,0x18000-0x4000,0x08000-0x8000,0x0C000-0xC000 }, // RAM6: 0 6 2 3
{ 0x00000-0x0000,0x1C000-0x4000,0x08000-0x8000,0x0C000-0xC000 }, // RAM7: 0 7 2 3
};
void mmu_update(void) // update the MMU tables with all the new offsets
{
// classic CPC RAM/ROM paging
int i=gate_ram&(gate_ram_depth?(4<<gate_ram_depth)-1:0),j;
if (gate_ram_dirty<(j=i?128+64*(i>>3):64)) // tag memory as dirty?
session_dirtymenu=gate_ram_dirty=j;
int k=(i>>3)<<16; i&=7; // k = bank offset, i = paging mode
// page 0x0000-0x3FFF
if ((j=mmu_ram_mode[i][0])>=0x10000-0x0000) j+=k;
mmu_ram[0]=&mem_ram[j];
mmu_rom[0]=(gate_mcr&4)?mmu_ram[0]:mmu_xtr[0]?&mem_xtr[0x0000-0x0000]:&mem_rom[0x0000-0x0000];
// page 0x4000-0x7FFF
if ((j=mmu_ram_mode[i][1])>=0x10000-0x4000) j+=k;
mmu_rom[1]=mmu_ram[1]=&mem_ram[j];
// page 0x8000-0xBFFF
if ((j=mmu_ram_mode[i][2])>=0x10000-0x8000) j+=k;
mmu_rom[2]=mmu_ram[2]=&mem_ram[j];
// page 0xC000-0xFFFF
if ((j=mmu_ram_mode[i][3])>=0x10000-0xC000) j+=k;
mmu_ram[3]=&mem_ram[j];
mmu_rom[3]=(gate_mcr&8)?mmu_ram[3]:(gate_rom<length(mmu_xtr)-1&&mmu_xtr[gate_rom+1]?&mem_xtr[0x4000+(gate_rom<<14)-0xC000]:(gate_rom!=7||disc_disabled)?&mem_rom[0x4000-0xC000]:&bdos_rom[0x0000-0xC000]);
if (plus_enabled)
{
if (!(gate_mcr&4)) // show low ROM?
{
mmu_rom[0]=mmu_xtr[0]?&mem_xtr[0x0000-0x0000]:&mem_rom[(plus_gate_mcr&7)<<14];
switch (plus_gate_mcr&24)
{
case 8:
mmu_rom[1]=&(mmu_rom[0])[0x0000-0x4000]; // show low ROM on page 1
mmu_rom[0]=mmu_ram[0]; // show RAM on page 0
break;
case 16:
mmu_rom[2]=&(mmu_rom[0])[0x0000-0x8000]; // show low ROM on page 2
mmu_rom[0]=mmu_ram[0]; // show RAM on page 0
break;
}
}
if (mmu_bit[1]=!(~plus_gate_mcr&24)) // show PLUS ASIC bank?
mmu_rom[1]=mmu_ram[1]=&plus_bank[0x0000-0x4000];
if (!(gate_mcr&8)) // show high ROM?
mmu_rom[3]=gate_rom<length(mmu_xtr)-1&&mmu_xtr[gate_rom+1]?&mem_xtr[0x4000+(gate_rom<<14)-0xC000]:
gate_rom<128?gate_rom==7?&mem_rom[0xC000-0xC000]:&mem_rom[0x4000-0xC000]:&mem_rom[((gate_rom&31)<<14)-0xC000];
}
else
mmu_bit[1]=0; // hide PLUS ASIC bank
#ifdef Z80_CPC_DANDANATOR // Dandanator is always the last part of the MMU update
if (mem_dandanator) // emulate the Dandanator (and more exactly its CPC-only memory map) only when a card is loaded
{
if (!(dandanator_cfg[5]&32)) // enabled?
{
if (!(dandanator_cfg[6]&32))
{
if (dandanator_cfg[5]&4) // the order is important; checking bit 0 first breaks "THE SWORD OF IANNA" when the first level begins
{
mmu_rom[2]=&mem_dandanator[((dandanator_cfg[6]&31)<<14)-0x8000];
//if ((dandanator_cfg[4]&2)&&(dandanator_cfg[6]&30)&&dandanator_canwrite) mmu_ram[2]=mmu_rom[2],dandanator_dirty=1;
}
else if (!(dandanator_cfg[5]&1)) // must check this for "MOJON TWINS ROMSET" to work
{
mmu_rom[0]=&mem_dandanator[((dandanator_cfg[6]&31)<<14)-0x0000];
if ((dandanator_cfg[4]&2)&&(dandanator_cfg[6]&30)&&dandanator_canwrite) // forbid writing on sectors 0 and 1 (!?)
//cprintf("R/W %02X%02X%02X%02X\n",dandanator_cfg[4],dandanator_cfg[5],dandanator_cfg[6],dandanator_cfg[7]),
mmu_ram[0]=mmu_rom[0],dandanator_dirty=1;
}
}
if (!(dandanator_cfg[7]&32))
{
if (dandanator_cfg[5]&8) // the order is important again: checking bit 1 first breaks "MOJON TWINS ROMSET" and other snapshot packs
{
mmu_rom[3]=&mem_dandanator[((dandanator_cfg[7]&31)<<14)-0xC000];
//if ((dandanator_cfg[4]&2)&&(dandanator_cfg[6]&30)&&dandanator_canwrite) mmu_ram[3]=mmu_rom[3],dandanator_dirty=1;
}
else //if (!(dandanator_cfg[5]&2)) // must NOT check this, otherwise "TESORO PERDIDO DE CUAUHTEMOC 64K" stops working
{
mmu_rom[1]=&mem_dandanator[((dandanator_cfg[7]&31)<<14)-0x4000];
//if ((dandanator_cfg[4]&2)&&(dandanator_cfg[6]&30)&&dandanator_canwrite) mmu_ram[1]=mmu_rom[1],dandanator_dirty=1;
}
}
}
else if (dandanator_cfg[5]&16) // "poor-man" rombox: "CPCSOCCER" overrides the current firmware with its own copy
{
if (!(gate_mcr&4)) mmu_rom[0]=&mem_dandanator[0x70000+((dandanator_cfg[4]&24)<<11)-0x0000];
if (!(gate_mcr&8)) mmu_rom[3]=&mem_dandanator[((dandanator_cfg[7]&31)<<14)-0xC000];
}
}
}
void dandanator_update(void)
{
//cprintf("DAN! %08X: %02X%02X,%02X,%02X\n",z80_pc.w,dandanator_cfg[4],dandanator_cfg[5],dandanator_cfg[6],dandanator_cfg[7]);
memcpy(&dandanator_cfg[4],&dandanator_cfg[0],4); mmu_update(); // update Dandanator state and MMU
}
#define z80_dandanator_0xFD(w) (dandanator_trap=dandanator_temp,dandanator_temp=w+3)
#define z80_dandanator_0xFD70(w,b) do{ if (dandanator_trap==w&&!(dandanator_cfg[5]&32)) { dandanator_cfg[2]=b; if (!(dandanator_cfg[1]&64)) dandanator_update(); } }while(0)
#define z80_dandanator_0xFD71(w,b) do{ if (dandanator_trap==w&&!(dandanator_cfg[5]&32)) { dandanator_cfg[3]=b; if (!(dandanator_cfg[1]&64)) dandanator_update(); } }while(0)
#define z80_dandanator_0xFD77(w,b) do{ if (dandanator_trap==w&&!(dandanator_cfg[5]&32)) { if (b&128) dandanator_cfg[1]=b; else dandanator_cfg[0]=b; if (!(dandanator_cfg[1]&64)) dandanator_update(); } }while(0)
#define z80_dandanator_0xC9() do{ if (dandanator_cfg[1]&64) { dandanator_cfg[1]&=~64; if (!(dandanator_cfg[5]&32)) dandanator_update(); } }while(0) // used by game packs, but not by "SWORD OF IANNA"
void z80_dandanator_reset(void)
{
MEMZERO(dandanator_cfg); dandanator_trap=dandanator_temp=0;
dandanator_cfg[3]=32; // default values are all ZERO but ZONE_1==32
dandanator_update();
#endif
}
INLINE void gate_table_select(BYTE i) { gate_index=(i&16)?16:(i&15); }
INLINE void gate_table_send(BYTE i)
{
gate_table[gate_index]=(i&=31);
video_clut_index=video_clut+gate_index;
if (!plus_enabled)
{
video_clut_value=video_table[video_type][i];
}
else
{
int j=video_asic_table[i]; // set both colour and the PLUS ASIC palette
video_clut_value=video_table[video_type][32+((j>>8)&15)]+video_table[video_type][48+((j>>4)&15)]+video_table[video_type][64+(j&15)];
mputii(&plus_palette[gate_index*2],j);
}
}
void video_clut_update(void) // precalculate palette following `video_type`
{
if (!plus_enabled)
for (int i=0;i<17;++i)
video_clut[i]=video_table[video_type][gate_table[i]];
else
for (int i=0;i<32;++i)
video_clut[i]=video_table[video_type][32+(plus_palette[i*2+1]&15)]+video_table[video_type][48+(plus_palette[i*2+0]>>4)]+video_table[video_type][64+(plus_palette[i*2+0]&15)];
video_clut_value=*(video_clut_index=video_clut+gate_index);
}
BYTE gate_mode0[2][256],gate_mode1[4][256]; // lookup table for byte->pixel conversion and Gate/CRTC exchanges
void gate_setup(void) // setup the Gate Array
{
for (int i=0;i<256;++i)
{
gate_mode0[0][i]=((i&128)?1:0)+((i&8)?2:0)+((i&32)?4:0)+((i&2)?8:0);
gate_mode0[1][i]=((i&64)?1:0)+((i&4)?2:0)+((i&16)?4:0)+((i&1)?8:0);
gate_mode1[0][i]=((i&128)?1:0)+((i&8)?2:0);
gate_mode1[1][i]=((i&64)?1:0)+((i&4)?2:0);
gate_mode1[2][i]=((i&32)?1:0)+((i&2)?2:0);
gate_mode1[3][i]=((i&16)?1:0)+((i&1)?2:0);
}
}
BYTE irq_delay; // 0 = INACTIVE, 1 = LINE 1, 2 = LINE 2, >2 = IRQ!
BYTE irq_timer; // Winape `R52`: rises from 0 to 52 (IRQ!)
int z80_irq; // Winape `ICSR`: B7 Raster (Gate Array / PRI), B6 DMA0, B5 DMA1, B4 DMA2 (top -- PRI DMA2 DMA1 DMA0 -- bottom)
int z80_active=0; // internal HALT flag: <0 EXPECT NMI!, 0 IGNORE IRQS, >0 ACCEPT IRQS, >1 EXPECT IRQ!
#define z80_nmi_throw (z80_active=-1,z80_irq|=256)
void gate_reset(void) // reset the Gate Array
{
gate_mcr=gate_ram=gate_rom=gate_index=irq_timer=irq_delay=0;
gate_ram_dirty=64;
MEMZERO(gate_table);
mmu_update();
}
// 0xF400-0xF700: PIO 8255 ------------------------------------------ //
BYTE pio_port_a,pio_port_b,pio_port_c,pio_control;
#define pio_setup()
void pio_reset(void)
{
pio_port_a=pio_port_b=pio_port_c=pio_control=0;
}
// behind the PIO: PSG AY-3-8910 ------------------------------------ //
#define PSG_TICK_STEP 8 // 1 MHz /2 /8 = 62500 Hz
#define PSG_KHZ_CLOCK 1000 // =16x
#define PSG_MAIN_EXTRABITS 0 // not even the mixer-banging beeper of "TERMINUS" needs >0
#if AUDIO_CHANNELS > 1
int psg_stereo[3][2]; const int psg_stereos[][3]={{0,0,0},{+256,0,-256},{+128,0,-128},{+64,0,-64}}; // A left, B middle, C right
#endif
#define PSG_PLAYCITY (2*PSG_KHZ_CLOCK) // base clock in kHz
//#define PSG_PLAYCITY_HALF // the PLAYCITY card contains two chips
int playcity_disabled=0,playcity_dirty,playcity_ctc_state[4]={0,0,0,0},playcity_ctc_flags[4]={0,0,0,0},playcity_ctc_count[4]={0,0,0,0},playcity_ctc_limit[4]={0,0,0,0};
int dac_disabled=1; // Digiblaster DAC, disabled by default to avoid trouble with the printer
#include "cpcec-ay.h"
// behind the PIO: TAPE --------------------------------------------- //
int tape_delay=0; // tape motor delay, in frames
#define tape_enabled (pio_port_c&16)
#define TAPE_MAIN_TZX_STEP (35<<0) // amount of T units per packet // highest value before "MARMALADE" breaks down is 197, but remainder isn't 0
//#define TAPE_OPEN_TAP_FORMAT // useless outside Spectrum
//#define TAPE_KANSAS_CITY // not too useful outside MSX...
#include "cpcec-k7.h"
// 0xFA7E, 0xFB7E, 0xFB7F: FDC 765 ---------------------------------- //
#define DISC_PARMTR_UNIT (disc_parmtr[1]&1) // CPC hardware is limited to two drives;
#define DISC_PARMTR_UNITHEAD (disc_parmtr[1]&5) // however, it allows two-sided discs.
#define DISC_TIMER_INIT ( 4<<6) // rough approximation: "PhX" requires 1<<7 at least and 8<<7 at most, but "Prehistorik 1" needs more than 1<<7.
#define DISC_TIMER_BYTE ( 2<<6) // rough approximation, too: the HEXAGON-protected "SWIV" needs at least 1<<6 and becomes very slow at 1<<8.
#define DISC_WIRED_MODE 0 // the CPC lacks the End-Of-Operation wire
#define DISC_PER_FRAME (312<<6) // = 1 MHz / 50 Hz ; compare with TICKS_PER_FRAME
#define DISC_CURRENT_PC (z80_pc.w)
#define DISC_NEW_SIDES 1
#define DISC_NEW_TRACKS 40
#define DISC_NEW_SECTORS 9
BYTE DISC_NEW_SECTOR_IDS[]={0xC1,0xC6,0xC2,0xC7,0xC3,0xC8,0xC4,0xC9,0xC5};
#define DISC_NEW_SECTOR_SIZE_FDC 2
#define DISC_NEW_SECTOR_GAPS 82
#define DISC_NEW_SECTOR_FILL 0xE5
#include "cpcec-d7.h"
// CPU-HARDWARE-VIDEO-AUDIO INTERFACE =============================== //
int audio_dirty,audio_queue=0; // used to clump audio updates together to gain speed
WORD gate_screen; // Gate Array's internal video address within the lowest 64K RAM, see below
int crtc_screen,crtc_raster,crtc_backup,crtc_double; // CRTC's internal video addresses, active and backup
int gate_count_r3x,gate_count_r3y,irq_steps; // Gate Array's horizontal and vertical timers filtering the CRTC's own
VIDEO_UNIT plus_sprite_border,*plus_sprite_target=NULL,plus_backup_pixels[3];
int plus_sprite_offset,plus_sprite_latest,plus_sprite_adjust;
void video_main_sprites(void)
{
int delta=plus_sprite_latest-plus_sprite_offset;
MEMLOAD(plus_backup_pixels,&plus_sprite_target[delta-3]);
for (int i=15*8;i>=0;i-=8) // render sprites
{
//if (i==plus_dirtysprite) continue;
int zoomy; if (!(zoomy=(plus_sprite_xyz[i+4]&3))) continue;
int zoomx; if (!(zoomx=(plus_sprite_xyz[i+4]>>2))) continue;
int spritey=(crtc_line-(plus_sprite_xyz[i+2]+256*plus_sprite_xyz[i+3]))&511; // 9-bit wrap!
if ((spritey>>=--zoomy)>=16) continue;
int spritex=(plus_sprite_xyz[i+0]+256*(signed char)plus_sprite_xyz[i+1])+plus_sprite_offset;
if (plus_sprite_latest>=spritex+(16<<--zoomx)||spritex>=video_pos_x) continue;
int x=0,xx=16;
if ((spritex-=plus_sprite_latest)<0)
x=(0-spritex)>>zoomx,xx-=x,spritex+=x<<zoomx; // clip left edge
BYTE *s=&plus_sprite_bmp[i*32+spritey*16+x];
VIDEO_UNIT *t=&plus_sprite_target[spritex+delta];
if (t+(xx<<zoomx)>video_target)
xx=((video_target-t-1)>>zoomx)+1; // clip right edge
switch (zoomx) // `xx` will never be zero!
{
case 0:
do
if (x=*s++)
*t=video_clut[16+x];
while (++t,--xx);
break;
case 1:
do
if (x=*s++)
t[0]=t[1]=video_clut[16+x];
while (t+=2,--xx);
break;
case 2:
do
if (x=*s++)
t[0]=t[1]=t[2]=t[3]=video_clut[16+x];
while (t+=4,--xx);
break;
}
}
MEMSAVE(&plus_sprite_target[delta-3],plus_backup_pixels); // hide sprite edges :-(
plus_sprite_latest=video_pos_x; //plus_dirtysprite=-1;
}
void video_main_borders(void)
{
if ((plus_sscr&128)&&plus_sprite_offset>VIDEO_OFFSET_X-16) // render extra border
for (int i=0;i<16;++i)
*plus_sprite_target++=plus_sprite_border;
video_target-=plus_sprite_adjust; // undo excess pixels
video_pos_x-=plus_sprite_adjust; // clip right border
plus_sprite_target=NULL;
plus_sprite_adjust=0;
}
void video_main(int t) // render video output for `t` clock ticks; t is always nonzero!
{
do {
// GATE ARRAY pixel rendering
if (!video_framecount&&video_pos_y>=VIDEO_OFFSET_Y&&video_pos_y<VIDEO_OFFSET_Y+VIDEO_PIXELS_Y)
{
if (video_pos_x>VIDEO_OFFSET_X-16&&video_pos_x<VIDEO_OFFSET_X+VIDEO_PIXELS_X)
{
#define VIDEO_NEXT *video_target++ // "VIDEO_NEXT = VIDEO_NEXT = ..." generates invalid code on VS13 and slower code on TCC
switch (gate_status)
{
VIDEO_UNIT p; BYTE b;
case 0: // MODE 0
p=video_clut[gate_mode0[0][b=mem_ram[gate_screen+0]]];
VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p;
p=video_clut[gate_mode0[1][b]];
VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p;
*video_clut_index=video_clut_value; // slow update
p=video_clut[gate_mode0[0][b=mem_ram[gate_screen+1]]];
VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p;
p=video_clut[gate_mode0[1][b]];
VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p;
break;
case 1: // MODE 1
p=video_clut[gate_mode1[0][b=mem_ram[gate_screen+0]]];
VIDEO_NEXT=p; VIDEO_NEXT=p;
p=video_clut[gate_mode1[1][b]];
VIDEO_NEXT=p; VIDEO_NEXT=p;
p=video_clut[gate_mode1[2][b]];
VIDEO_NEXT=p; VIDEO_NEXT=p;
p=video_clut[gate_mode1[3][b]];
VIDEO_NEXT=p; VIDEO_NEXT=p;
*video_clut_index=video_clut_value; // slow update
p=video_clut[gate_mode1[0][b=mem_ram[gate_screen+1]]];
VIDEO_NEXT=p; VIDEO_NEXT=p;
p=video_clut[gate_mode1[1][b]];
VIDEO_NEXT=p; VIDEO_NEXT=p;
p=video_clut[gate_mode1[2][b]];
VIDEO_NEXT=p; VIDEO_NEXT=p;
p=video_clut[gate_mode1[3][b]];
VIDEO_NEXT=p; VIDEO_NEXT=p;
break;
case 2: // MODE 2
VIDEO_NEXT=video_clut[(b=mem_ram[gate_screen+0])>>7];
VIDEO_NEXT=video_clut[(b>>6)&1];
VIDEO_NEXT=video_clut[(b>>5)&1];
VIDEO_NEXT=video_clut[(b>>4)&1];
VIDEO_NEXT=video_clut[(b>>3)&1];
VIDEO_NEXT=video_clut[(b>>2)&1];
VIDEO_NEXT=video_clut[(b>>1)&1];
VIDEO_NEXT=video_clut[b&1];
*video_clut_index=video_clut_value; // slow update
VIDEO_NEXT=video_clut[(b=mem_ram[gate_screen+1])>>7];
VIDEO_NEXT=video_clut[(b>>6)&1];
VIDEO_NEXT=video_clut[(b>>5)&1];
VIDEO_NEXT=video_clut[(b>>4)&1];
VIDEO_NEXT=video_clut[(b>>3)&1];
VIDEO_NEXT=video_clut[(b>>2)&1];
VIDEO_NEXT=video_clut[(b>>1)&1];
VIDEO_NEXT=video_clut[b&1];
break;
case 3: // MODE 3
p=video_clut[gate_mode1[0][b=mem_ram[gate_screen+0]]];
VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p;
p=video_clut[gate_mode1[1][b]];
VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p;
*video_clut_index=video_clut_value; // slow update
p=video_clut[gate_mode1[0][b=mem_ram[gate_screen+1]]];
VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p;
p=video_clut[gate_mode1[1][b]];
VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p;
break;
case 4: case 5: case 6: case 7: case 8: case 9: case 10:
case 11: case 12: case 13: case 14: case 15: case 16: case 17:
case 18: case 19: case 20: case 21: case 22: case 23: case 24:
case 25: case 26: case 27: case 28: case 29: case 30: case 31: // BORDER
p=video_clut[16];
VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p;
*video_clut_index=video_clut_value; // slow update
p=video_clut[16];
VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p;
break;
default: // HBLANK/VBLANK: BLANK BLACK!
p=video_table[video_type][20]; // BLACK from the colour table
VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p;
VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p; VIDEO_NEXT=p;
*video_clut_index=video_clut_value; // slow update
break;
}
}
else // drawing, but not now
video_target+=16,*video_clut_index=video_clut_value; // slow update
video_pos_x+=16; // update the cursor regardless of activity
// special pixel rendering cases: start and end of bitmap rasterline
if (crtc_status&(CRTC_STATUS_V_OFF+CRTC_STATUS_VSYNC)) // these events only make sense inside the bitmap!
;
else if (crtc_table[1]) // these events only make sense if the bitmap size is nonzero!
{
if (!crtc_count_r0) // beginning of bitmap -- CRTC_STATUS_H_OFF_RES won't do because of retriggering, f.e. "SYNERGY 2"
{
if (plus_enabled)
{
if (plus_sprite_target)
{
if (video_pos_x>plus_sprite_latest) video_main_sprites(); // draw more sprites, "DELIRIUM" retriggers the horizontal bitmap!
video_main_borders(); // retrigger border cleanup
}
plus_sprite_border=video_clut[16];
plus_sprite_target=video_target;
plus_sprite_offset=video_pos_x;
plus_sprite_adjust=plus_gate_enabled?plus_sscr&15:gate_status&2?0:1; // "IMPERIAL MAHJONG" on PLUS relies on this!
if (video_pos_x>VIDEO_OFFSET_X-16&&video_pos_x<VIDEO_OFFSET_X+VIDEO_PIXELS_X)
{
VIDEO_UNIT p=gate_status<32?video_clut[16]:video_table[video_type][20];
for (int i=0;i<plus_sprite_adjust;++i)
VIDEO_NEXT=p; // pad left border
}
else
video_target+=plus_sprite_adjust;
plus_sprite_latest=video_pos_x+=plus_sprite_adjust;
}
else if (!(crtc_type&5)&&video_pos_x>VIDEO_OFFSET_X) // CRTC0 and CRTC2 draw "shadows" on SYNERGY 2 (5 stripes) and
video_target[-8]= video_target[-7]= video_target[-6]= video_target[-5]= // ONESCREEN COLONIES (brick wall):
video_target[-4]= video_target[-3]= video_target[-2]= video_target[-1]= video_clut[16]; // actually the border
}
else if (crtc_table[1]==crtc_count_r0) // end of bitmap -- CRTC_STATUS_H_OFF_SET will do
if (plus_sprite_target)
{
if (video_pos_x>plus_sprite_latest) video_main_sprites(); // last sprites
video_main_borders(); // border cleanup
}
}
}
else // not drawing at all!!
video_pos_x+=16,video_target+=16,*video_clut_index=video_clut_value; // slow update
hsync_count+=16;
gate_screen=crtc_screen+crtc_raster;
// GATE ARRAY slow reactions to CRTC events
if (crtc_before!=crtc_status) // speedup: no need to test nonextant events, this is true only 1 out of 6 times (more events should be moved here)
{
if (plus_pri==crtc_line&&plus_pri) // the PLUS ASIC handles the programmable raster interrupt (PRI) here:
if ((~crtc_before&crtc_status&CRTC_STATUS_HSYNC) // the IRQ triggers on CRTC_STATUS_HSYNC_SET (normal)
||(!crtc_count_r0&&crtc_before&CRTC_STATUS_HSYNC)) // or CRTC_STATUS_H_OFF_RES during HSYNC (early)
z80_irq|=128;