Add examples and insights that demonstrates Classiq's HW-aware synthesis capability

[arielsmoler]

In this issue, we will add practical examples to demonstrate Classiq's Hardware-Aware Synthesis capability.

Quantum computers differ from one other in many significant parameters, such as basis gates, connectivity, and error rates. The device specifications determine the possibility of executing the quantum program, and logically equivalent programs might require different implementations to optimize the probability of success.

The Classiq platform allows you to provide information about the hardware you want to use to run your quantum program. The synthesis engine takes the parameters of this hardware into account. For example, the engine could choose the implementation of a function that requires the least number of swaps, given the connectivity of the hardware.

In this issue we will synthesize a simple MCX circuit with at least 2 different HW-aware configuration settings and examine the differences in their implementations.

To complete this issue, follow these steps:

1. Create a new jupyter notebook (.ipynb file). Use any jupyter editor (e.g. jupyter lab, google colab, etc).
2. Similar to the HW-aware Synthesis of MCX notebook, create a new notebook that implements a multiple control-x (MCX) logic and sets 2 different HW-aware synthesis preferences configurations (other than the ones used in the notebook linked above).
3. Synthesize your MCX circuit with the 2 HW-aware synthesis preferences, view the implementation result and write a short paragraph with your insights.
4. After creating the notebook, make sure you insert the write_qmod(model, "hardware_aware_YOUR_CONFIGURATION_NAME.qmod") line. Run the notebook, and you will automatically generate the .qmod file for this example.
5. Make sure the notebook looks well, does not have any typos / mistakes, and is running properly.

Follow the contribution guidelines to open a pull request. Submit the tutorial to the directory: classiq-library/community/basic_examples/hw_aware_synthesis

[Qubit1718]

Hi @amir-naveh @arielsmoler,

I have solved the issue. But before creating a PR, I want to understand if there are any specific requirements for preferences configurations, like the backend, device, basis_gates, etc.

[Qubit1718]

Hi @amir-naveh @arielsmoler,

Please review the PR #116 and let me know if there is anything missing. I hope to hear from you soon!

[Qubit1718]

Hi @orsa-classiq,

To get the UnitaryHack bounty, the issue must be assigned to the person. Can you please assign this issue to me? Also, the issue must be connected to the PR it seems.
I hope you understand.
Thanks!