If you want more information about the implementation, you could read - or at least try, unfortunately, is in greek language - this report file Milestone 2 or by reading the inline documentation.
Block diagrams are able to be changed:
This project was developed using Xilinx Vivado HLS 2017.4
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Open Vivado HLS 2017.4 and using it open reference project
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Open the reference Project by going to the File -> Open project
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Replace the source files of your reference project with those from our project src
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Import Files if needed by right clicking the Source and selecting Add Files
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Completed
- Go to the bar in the top of Vivado and select the Run C Simulation
(Simulation screenshots are included here)
This folder contains the exported IP in order to use it in Vivado 2017.4