{"payload":{"header_redesign_enabled":false,"results":[{"id":"685841079","archived":false,"color":"#b2b7f8","followers":0,"has_funding_file":false,"hl_name":"BoooC/HDL_HW","hl_trunc_description":null,"language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":685841079,"name":"HDL_HW","owner_id":159609862,"owner_login":"BoooC","updated_at":"2024-01-18T12:16:46.708Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":53,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253ABoooC%252FHDL_HW%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/BoooC/HDL_HW/star":{"post":"cxdDjA-FT6yTXFGlZDJgtdcHZkroDumvXtkugmmaFSX7eeQjbzBIvNzg8I9FZIgAepP6IVdS5vw5ISRNQOekGw"},"/BoooC/HDL_HW/unstar":{"post":"AswoYFvW-8KO90qIDFqqbll5v_wylhOstNBettK9VBCD92vqZnf3eTRPAFaD_F4yKjcsuFBE6AtBt3weO4aPLA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"s3DvLHNg65lQ-n68zYaHzdnfA9MS9WEEEYUEcRHyoKXNautwjEiKcTTj8N7PUJraU0rCkg_dhoylxKmM_pgaQQ"}}},"title":"Repository search results"}