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JaredWrightJaredWright
authored
Merge pull request #77 from jaysongiroux/amd_VMCB_PR
Amd vmcb
2 parents 52266a6 + b1f5b68 commit 485b7f2

31 files changed

+1564
-17
lines changed

‎data/amd/register/vmcb/000h.yml

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
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long_name: "000h (vector 0)"
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purpose: |
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"
5-
Intercept reads of CR0–15, respectively
5+
000h
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"
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size: 32
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arch: amd64
@@ -17,21 +17,21 @@
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component: vmcb
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fieldsets:
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name: latest
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condition: "Fieldset valid on latest version of the AMD architecture"
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size: 32
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- name: latest
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condition: "Fieldset valid on latest version of the AMD architecture"
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size: 32
2323

24-
fields:
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- name: "Bits 15_0"
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long_name: "Intercept reads of CR0–15, respectively"
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lsb: 0
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msb: 15
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readable: True
30-
writable: True
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fields:
25+
- name: "Bits 15_0"
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long_name: "Intercept reads of CR0–15, respectively"
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lsb: 0
28+
msb: 15
29+
readable: True
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writable: True
3131

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- name: "Bits 31_16"
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long_name: "Intercept writes of CR0–15, respectively"
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lsb: 16
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msb: 31
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readable: True
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writable: True
32+
- name: "Bits 31_16"
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long_name: "Intercept writes of CR0–15, respectively"
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lsb: 16
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msb: 31
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readable: True
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writable: True

‎data/amd/register/vmcb/004h.yml

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
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- name: 004h
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long_name: "004h (vector 1)"
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purpose: |
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"
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004h
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"
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size: 32
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arch: amd64
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access_mechanisms:
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- name: read
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offset: 0x004
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component: vmcb
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15+
- name: write
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offset: 0x004
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component: vmcb
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fieldsets:
20+
- name: latest
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condition: "Fieldset valid on latest version of the AMD architecture"
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size: 32
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fields:
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- name: "Bits 15_0"
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long_name: "Intercept reads of DR0–15, respectively"
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lsb: 0
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msb: 15
29+
readable: True
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writable: True
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- name: "Bits 31_16"
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long_name: "Intercept writes of DR0–15, respectively"
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lsb: 16
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msb: 31
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readable: True
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writable: True

‎data/amd/register/vmcb/008h.yml

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
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- name: 008h
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long_name: "008h (vector 2)"
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purpose: |
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"
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008h
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Intercept exception vectors 0–31, respectively.
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"
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size: 32
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arch: amd64
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12+
access_mechanisms:
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- name: read
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offset: 0x008
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component: vmcb
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- name: write
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offset: 0x008
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component: vmcb
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fieldsets:
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- name: latest
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condition: "Fieldset valid on latest version of the AMD architecture"
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size: 32
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fields:
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- name: "Bits 31_0"
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long_name: "Intercept exception vectors 0–31, respectively."
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lsb: 0
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msb: 31
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readable: True
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writable: True

‎data/amd/register/vmcb/00Ch.yml

Lines changed: 249 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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- name: 00Ch
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long_name: "00Ch (vector 3)"
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purpose: |
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"
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00Ch (vector 3)
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"
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size: 32
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arch: amd64
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access_mechanisms:
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- name: read
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offset: 0x00C
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component: vmcb
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- name: write
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offset: 0x00C
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component: vmcb
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fieldsets:
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- name: latest
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condition: "Fieldset valid on latest version of the AMD architecture"
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size: 32
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fields:
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- name: "Bits 0"
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long_name: "Intercept INTR (physical maskable interrupt)."
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lsb: 0
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msb: 0
29+
readable: True
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writable: True
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- name: "Bits 1"
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long_name: "Intercept NMI."
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lsb: 1
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msb: 1
36+
readable: True
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writable: True
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- name: "Bits 2"
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long_name: "Intercept SMI."
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lsb: 2
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msb: 2
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readable: True
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writable: True
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- name: "Bits 3"
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long_name: "Intercept INIT."
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lsb: 3
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msb: 3
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readable: True
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writable: True
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- name: "Bits 4"
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long_name: "Intercept VINTR (virtual maskable interrupt)."
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lsb: 4
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msb: 4
57+
readable: True
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writable:
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- name: "Bits 5"
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long_name: "Intercept CR0 writes that change bits other than CR0.TS or CR0.MP."
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lsb: 5
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msb: 5
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readable: True
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writable: True
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- name: "Bits 6"
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long_name: "Intercept reads of IDTR."
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lsb: 6
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msb: 6
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readable: True
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writable: True
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- name: "Bits 7"
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long_name: "Intercept reads of GDTR."
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lsb: 7
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msb: 7
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readable: True
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writable: True
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- name: "Bits 8"
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long_name: "Intercept reads of LDTR."
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lsb: 8
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msb: 8
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readable: True
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writable: True
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- name: "Bits 9"
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long_name: "Intercept reads of TR"
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lsb: 9
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msb: 9
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readable: True
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writable: True
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- name: "Bits 10"
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long_name: "Intercept writes of IDTR."
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lsb: 10
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msb: 10
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readable: True
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writable: True
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- name: "Bits 11"
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long_name: "Intercept writes of GDTR."
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lsb: 11
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msb: 11
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readable: True
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writable: True
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- name: "Bits 12"
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long_name: "Intercept writes of LDTR."
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lsb: 12
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msb: 12
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readable: True
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writable: True
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- name: "Bits 13"
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long_name: "Intercept writes of TR."
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lsb: 13
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msb: 13
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readable: True
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writable: True
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- name: "Bits 14"
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long_name: "Intercept RDTSC instruction."
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lsb: 14
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msb: 14
127+
readable: True
128+
writable: True
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- name: "Bits 15"
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long_name: "Intercept RDPMC instruction."
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lsb: 15
133+
msb: 15
134+
readable: True
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writable: True
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- name: "Bits 16"
138+
long_name: "Intercept PUSHF instruction."
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lsb: 16
140+
msb: 16
141+
readable: True
142+
writable: True
143+
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- name: "Bits 17"
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long_name: "Intercept POPF instruction"
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lsb: 17
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msb: 17
148+
readable: True
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writable: True
150+
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- name: "Bits 18"
152+
long_name: "Intercept CPUID instruction."
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lsb: 18
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msb: 18
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readable: True
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writable: True
157+
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- name: "Bits 19"
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long_name: "Intercept RSM instruction."
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lsb: 19
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msb: 19
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readable: True
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writable: True
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- name: "Bits 20"
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long_name: "Intercept IRET instruction."
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lsb: 20
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msb: 20
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readable: True
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writable: True
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- name: "Bits 21"
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long_name: "Intercept INTn instruction."
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lsb: 21
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msb: 21
176+
readable: True
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writable: True
178+
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- name: "Bits 22"
180+
long_name: "Intercept INVD instruction."
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lsb: 22
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msb: 22
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readable: True
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writable: True
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- name: "Bits 23"
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long_name: "Intercept PAUSE instruction."
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lsb: 23
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msb: 23
190+
readable: True
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writable: True
192+
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- name: "Bits 24"
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long_name: "Intercept HLT instruction."
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lsb: 24
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msb: 24
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readable: True
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writable: True
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- name: "Bits 25"
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long_name: "Intercept INVLPG instruction."
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lsb: 25
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msb: 25
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readable: True
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writable: True
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- name: "Bits 26"
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long_name: "Intercept INVLPGA instruction."
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lsb: 26
210+
msb: 26
211+
readable: True
212+
writable: True
213+
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- name: "Bits 27"
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long_name: "IOIO_PROT—Intercept IN/OUT accesses to selected ports."
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lsb: 27
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msb: 27
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readable: True
219+
writable: True
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- name: "Bits 28"
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long_name: "MSR_PROT—intercept RDMSR or WRMSR accesses to selected MSRs."
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lsb: 28
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msb: 28
225+
readable: True
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writable: True
227+
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- name: "Bits 29"
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long_name: "Intercept task switches."
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lsb: 29
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msb: 29
232+
readable: True
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writable: True
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- name: "Bits 30"
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long_name: "FERR_FREEZE: intercept processor “freezing” during legacy FERR handling."
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lsb: 30
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msb: 30
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readable: True
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writable: True
241+
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- name: "Bits 31"
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long_name: "Intercept shutdown events."
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lsb: 31
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msb: 31
246+
readable: True
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writable: True
248+
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