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tangxifantangxifan
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2 parents 11cf30b + 7860042 commit 70b66e0

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4 files changed

+114
-47
lines changed

4 files changed

+114
-47
lines changed

‎vpr7_x2p/libarchfpga/SRC/include/physical_types.h

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -319,6 +319,10 @@ struct s_interconnect {
319319
char *output_string;
320320
/* Baudouin Chauviere: SDC generation */
321321
char *loop_breaker_string;
322+
char *loop_breaker_delay_first_segment_min;
323+
char *loop_breaker_delay_first_segment_max;
324+
char *loop_breaker_delay_second_segment_min;
325+
char *loop_breaker_delay_second_segment_max;
322326
/* END */
323327

324328
t_pin_to_pin_annotation *annotations; /* [0..num_annotations-1] */
@@ -545,8 +549,10 @@ struct s_pb_graph_edge {
545549
boolean is_disabled;
546550
int nb_mux;
547551
int nb_pin;
548-
char* delay_first_segment;
549-
char* delay_second_segment;
552+
char* delay_first_segment_max;
553+
char* delay_second_segment_max;
554+
char* delay_first_segment_min;
555+
char* delay_second_segment_min;
550556
/* END */
551557
};
552558
typedef struct s_pb_graph_edge t_pb_graph_edge;

‎vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1411,6 +1411,35 @@ static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) {
14111411
mode->interconnect[i].loop_breaker_string= my_strdup(Prop);
14121412
}
14131413
ezxml_set_attr(Cur, "loop_breaker", NULL);
1414+
1415+
Cur2 = FindFirstElement(Cur, "delay_first_segment", FALSE);
1416+
if (NULL != Cur2) {
1417+
Prop = FindProperty(Cur2, "min", FALSE);
1418+
if (NULL != Prop) {
1419+
mode->interconnect[i].loop_breaker_delay_first_segment_min = my_strdup(Prop);
1420+
ezxml_set_attr(Cur2, "min", NULL);
1421+
}
1422+
Prop = FindProperty(Cur2, "max", FALSE);
1423+
if (NULL != Prop) {
1424+
mode->interconnect[i].loop_breaker_delay_first_segment_max = my_strdup(Prop);
1425+
ezxml_set_attr(Cur2, "max", NULL);
1426+
}
1427+
FreeNode(Cur2);
1428+
}
1429+
Cur2 = FindFirstElement(Cur, "delay_second_segment", FALSE);
1430+
if (NULL != Cur2) {
1431+
Prop = FindProperty(Cur2, "min", FALSE);
1432+
if (NULL != Prop) {
1433+
mode->interconnect[i].loop_breaker_delay_second_segment_min = my_strdup(Prop);
1434+
ezxml_set_attr(Cur2, "min", NULL);
1435+
}
1436+
Prop = FindProperty(Cur2, "max", FALSE);
1437+
if (NULL != Prop) {
1438+
mode->interconnect[i].loop_breaker_delay_second_segment_max = my_strdup(Prop);
1439+
ezxml_set_attr(Cur2, "max", NULL);
1440+
}
1441+
FreeNode(Cur2);
1442+
}
14141443
/* END */
14151444

14161445
/* Process delay and capacitance annotations */

‎vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.c

Lines changed: 26 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -55,51 +55,24 @@ void sdc_dump_annotation(char* from_path, // includes the cell
5555
FILE* fp,
5656
t_pb_graph_edge* cur_edge){
5757

58-
//char* min_value = NULL;
59-
t_interconnect* cur_interconnect;
60-
float max_value = NULL;
58+
float min_value = 0;
59+
float max_value = 0;
6160
int i,j;
6261

6362
// Find in the annotations the min and max
64-
65-
cur_interconnect = cur_edge->interconnect;
66-
for (i=0; i < cur_interconnect->num_annotations; i++) {
67-
if (E_ANNOT_PIN_TO_PIN_DELAY == cur_interconnect->annotations[i].type) {
68-
for (j=0; j < cur_interconnect->annotations[i].num_value_prop_pairs; j++) {
69-
/* if (E_ANNOT_PIN_TO_PIN_DELAY_MIN == interconnect->annotations[i].prop[j]) {
70-
min_value = cur_edge->delay_min;
71-
min_value = max_value*pow(10,9);
72-
}*/
73-
if(E_ANNOT_PIN_TO_PIN_DELAY_MAX == cur_interconnect->annotations[i].prop[j]) {
74-
max_value = cur_edge->delay_max;
75-
max_value = max_value*pow(10,9); /* converts sec in ns */
76-
}
77-
}
78-
}
63+
if (0 != cur_edge->delay_min) {
64+
min_value = cur_edge->delay_min;
65+
min_value = min_value*pow(10,9);
66+
fprintf (fp, "set_min_delay -combinational_from_to -from %s -to %s ", from_path, to_path);
67+
fprintf (fp,"%f\n", min_value);
7968
}
80-
81-
82-
// Dump the annotation
83-
// If no annotation was found, dump 0
84-
85-
/* fprintf (fp, "set_min_delay -from %s -to %s ", from_path,to_path);
86-
if (NULL != min_value) {
87-
fprintf(fp, "%s\n", min_value);
88-
} else {
89-
fprintf(fp, "0\n");
90-
} */
91-
92-
/*fprintf (fp, "set_max_delay -from %s -to %s ", from_path, to_path);
93-
if (max_value != NULL){
94-
fprintf (fp,"%s\n",max_value);
95-
} else {
96-
fprintf (fp,"0\n");
97-
}*/
98-
if (max_value != NULL){
99-
fprintf (fp, "set_max_delay -combinational_from_to -from %s -to %s ", from_path, to_path);
100-
fprintf (fp,"%f\n", max_value);
101-
}
102-
return;
69+
if (0 != cur_edge->delay_max) {
70+
max_value = cur_edge->delay_max;
71+
max_value = max_value*pow(10,9);
72+
fprintf (fp, "set_max_delay -combinational_from_to -from %s -to %s ", from_path, to_path);
73+
fprintf (fp,"%f\n", max_value);
74+
}
75+
return;
10376
}
10477

10578

@@ -278,14 +251,22 @@ void dump_sdc_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
278251
sprintf(set_disable_path, "%s/%s_%d_", input_buffer_path, input_buffer_name,
279252
des_pb_graph_pin->input_edges[iedge]->nb_pin);
280253

281-
if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_first_segment) {
254+
if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_first_segment_min) {
255+
fprintf (fp, "set_min_delay -from %s -to %s/%s %s \n", from_path, set_disable_path, input_buffer_in,
256+
des_pb_graph_pin->input_edges[iedge]->delay_first_segment_min);
257+
}
258+
if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_first_segment_max) {
282259
fprintf (fp, "set_max_delay -from %s -to %s/%s %s \n", from_path, set_disable_path, input_buffer_in,
283-
to_path, des_pb_graph_pin->input_edges[iedge]->delay_first_segment);
260+
des_pb_graph_pin->input_edges[iedge]->delay_first_segment_max);
284261
}
285262
fprintf (fp, "set_disable_timing -from %s -to %s %s \n", input_buffer_in, input_buffer_out, set_disable_path);
286-
if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_second_segment) {
263+
if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_second_segment_min) {
264+
fprintf (fp, "set_min_delay -from %s/%s -to %s %s \n", set_disable_path, input_buffer_out,
265+
to_path, des_pb_graph_pin->input_edges[iedge]->delay_second_segment_min);
266+
}
267+
if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_second_segment_max) {
287268
fprintf (fp, "set_max_delay -from %s/%s -to %s %s \n", set_disable_path, input_buffer_out,
288-
to_path, des_pb_graph_pin->input_edges[iedge]->delay_second_segment);
269+
to_path, des_pb_graph_pin->input_edges[iedge]->delay_second_segment_max);
289270
}
290271
my_free(input_buffer_path);
291272
my_free(set_disable_path);

‎vpr7_x2p/vpr/SRC/pack/pb_type_graph.c

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2070,6 +2070,23 @@ static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num,
20702070
i_num_output_edges ++) {
20712071
if (cur_interc == cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) {
20722072
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE;
2073+
2074+
if (NULL != cur_interc->loop_breaker_delay_first_segment_min) {
2075+
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_min
2076+
= cur_interc->loop_breaker_delay_first_segment_min;
2077+
}
2078+
if (NULL != cur_interc->loop_breaker_delay_first_segment_max) {
2079+
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_max
2080+
= cur_interc->loop_breaker_delay_first_segment_max;
2081+
}
2082+
if (NULL != cur_interc->loop_breaker_delay_second_segment_min) {
2083+
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_min
2084+
= cur_interc->loop_breaker_delay_second_segment_min;
2085+
}
2086+
if (NULL != cur_interc->loop_breaker_delay_second_segment_max) {
2087+
cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_max
2088+
= cur_interc->loop_breaker_delay_second_segment_max;
2089+
}
20732090
}
20742091
}
20752092
break;
@@ -2079,6 +2096,23 @@ static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num,
20792096
i_num_output_edges ++) {
20802097
if (cur_interc == cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) {
20812098
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE;
2099+
2100+
if (NULL != cur_interc->loop_breaker_delay_first_segment_min) {
2101+
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_min
2102+
= cur_interc->loop_breaker_delay_first_segment_min;
2103+
}
2104+
if (NULL != cur_interc->loop_breaker_delay_first_segment_max) {
2105+
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_max
2106+
= cur_interc->loop_breaker_delay_first_segment_max;
2107+
}
2108+
if (NULL != cur_interc->loop_breaker_delay_second_segment_min) {
2109+
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_min
2110+
= cur_interc->loop_breaker_delay_second_segment_min;
2111+
}
2112+
if (NULL != cur_interc->loop_breaker_delay_second_segment_max) {
2113+
cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_max
2114+
= cur_interc->loop_breaker_delay_second_segment_max;
2115+
}
20822116
}
20832117
}
20842118
break;
@@ -2088,6 +2122,23 @@ static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num,
20882122
i_num_output_edges ++) {
20892123
if (cur_interc == cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) {
20902124
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE;
2125+
2126+
if (NULL != cur_interc->loop_breaker_delay_first_segment_min) {
2127+
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_min
2128+
= cur_interc->loop_breaker_delay_first_segment_min;
2129+
}
2130+
if (NULL != cur_interc->loop_breaker_delay_first_segment_max) {
2131+
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_max
2132+
= cur_interc->loop_breaker_delay_first_segment_max;
2133+
}
2134+
if (NULL != cur_interc->loop_breaker_delay_second_segment_min) {
2135+
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_min
2136+
= cur_interc->loop_breaker_delay_second_segment_min;
2137+
}
2138+
if (NULL != cur_interc->loop_breaker_delay_second_segment_max) {
2139+
cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_max
2140+
= cur_interc->loop_breaker_delay_second_segment_max;
2141+
}
20912142
}
20922143
}
20932144
break;

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