@@ -24,7 +24,7 @@ The ultra-condensed description of how to use it is:
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In slightly more detail, the initial script is written in a sort of
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pseudo-Verilog. This defines several modules, each of which will be
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- turned into an actual Verilog module running ` acov ` . The code in these
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+ turned into an actual Verilog module by running ` acov ` . The code in these
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auto-generated modules contains DPI calls to a library (also included
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with ACov) called ` libacovdpi.so ` . These calls basically say "Hey,
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I've just seen the following coverage group with the following value".
@@ -53,6 +53,9 @@ An ACov input file might look like this:
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record bar cover bits;
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}
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+ Where the inputs ` foo ` , ` bar ` , etc. correspond to internal or external
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+ signals of the module ` xxx ` that you want to cover.
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+
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This will create a Verilog module called ` xxx_coverage ` , of the
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following form:
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@@ -284,6 +287,12 @@ means something akin to toggle coverage: we want to see each bit of
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the signal equal to zero and equal to one. For a signal of width W,
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specifying ` cover bits ` gives ` 2 * W ` bins.
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+ Further ` record ` examples:
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+ record c == 4'd10 as c_ten; // where c is 4-bit
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+ record d[1:0] as d_LSBs cover {0..2};
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+ record e[8:6] > 3'd5 && |f as e_thresh cover {1};
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+
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### Groups
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To specify a cross of multiple signals, use the ` group ` keyword. For
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